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60607hkim 20061221-s00013 no.a0569-1/106 lc74736pt overview the lc74736pt is an on-screen display cmos ic that displa ys characters and patterns on a tv screen under the control of a microcontroller. for qvga display, the lc74736pt supports the use of both a 16 16 dot character font and a 16 16 dot graphic font with 16 colors. for wvga display, the lc74736pt supports the use of both a 24 32 dot character font and a 24 32 dot graphic font with 16 colors. the lc74736pt can also implement extremely varied displays by the use of an external rom. the lc74736pt supports both qvga (480 234) and wvga (800 480). features (1) screen structure main: 2 screens (1 scr een for wvga display) 30 characters 15 lines (up to 450 characters) on a qvga panel 33 characters 15 lines (up to 495 characters) on a wvga panel (up to 34 characters 18 lines) wallpaper display screen: qvga mode: maximum permanent repetition of a 4 4 (horizontal vertical) character pattern wvga mode: maximum permanent repetition of a 2 2 (horizontal vertical) character pattern ordering number : ena0569a cmos ic on-screen display controller specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
lc74736pt no.a0569-2/106 (2) character structure qvga mode: about 9mhz 16 dots (horizontal) 16 dots (vertical): character display 16 dots (horizontal) 16 dots (vertical): graphic glyph display wvga mode: about 33.2mhz 24 dots (horizontal) 32 dots (vertical): character display 24 dots (horizontal) 32 dots (vertical): graphic glyph display character display clock: lc oscillator (about 10mhz) external clock signal input (up to 40mhz) built-in pll (vco) (7 to 40mhz) (3) number of characters qvga mode up to 16384 characters when an external 16-bit 16m rom is used. wvga mode up to 4096 characters when an external 16-bit 16m rom is used. no internal rom internal character ram qvga: 4 characters, wvga: 1 character (4) character sizes: four horizontal sizes (1 , 2 , 3 , and 4 ) four vertical sizes (1 , 2 , 3 , and 4 ) (the character size is specified in line units.) (5) display start positions: 1024 positions in the horizontal direction and 512 positions in the vertical direction. setting units: horizontal: 1 dot (in screen units) vertical: 1 dot (in screen units) (6) display functions ? blinking specification (in character units) period: 1/64, 1/32, and 1/16 of the vertical sync signal (in screen units) duty: fixed at 50% ? box (raised or recessed) display raised/recessed specification (in character units) left: off/on specification (in character units) right: off/on specification (in character units) top: off/on specification (in character units) bottom: off/on specification (in character units) ? border specification (in line units): only valid with glyphs from the character font. (7) color specification character ? character color (in character units): 1 of 16 colors can be specified. ? character background color (i n character units): 1 of 16 colors can be specified. ? border color (in line units): 1 of 16 colors can be specified. graphic ? 16 types can be specified by rom data graphic 2 ? 16 types can be specified by rom data 1 color type can be changed. graphic 3 ? 16 types can be specified by rom data 1 color table type can be changed. ? box (raised or recessed) co lor (line units): 1 of 16 colors can be specified. ? background color (screen units): 1 of 16 colors can be specified.
lc74736pt no.a0569-3/106 (8) color table (palette) ? sixteen colors can be selected from a set of 4096 co lors (one of which is speci fied to be transparent.) ? number of color tables: 4. this allows up to 64 colors to be displayed at the same time. (9) wallpaper screen (graphics glyphs only) wallpaper display: repeated di splay under the main screen (up to 4 characters horizontally by 4 characters vertically). sprite character display: displayed above the main screen (up to 4 characters horizontally by 4 characters vertically). (10) line spacing control 0-15 scan lines (in line units) (11) output analog rgb output( to 20mhz) digital rgb output (4 bits per color) blk (osd display period signal) package: tqfp100 voltage: 3.3v package dimensions unit : mm (typ) 3274 sanyo : tqfp100(14x14) 100 125 26 50 51 75 76 14.0 (1.0) (1.0) 0.1 0.125 16.0 0.2 0.5 1.2max 0.5 14.0 16.0
lc74736pt no.a0569-4/106 pin assignment v dd 3 v ss 3 a0 a1 a2 a3 a4 a5 a6 a7 v dd 3 v ss 3 a8 a9 a10 a11 a12 a13 a14 a15 v dd 3 v ss 3 a16 a17 a18 v ss 1 v dd 1 oscin oscout extclk ctrl1 sclk sin cs vsync hsync test1 test2 rst clkout v ss 1 nc nc nc nc nc v ss 4 pd0 vcor v dd 4 a 19 ce oe v dd 3 v ss 3 v dd 1 v ss 1 d0 d1 d2 d3 d4 d5 d6 d7 v dd 1 v ss 1 d8 d9 d10 d11 d12 d13 d14 d15 1 bfin bfout rd3 rd2 rd1 rd0 gd3 gd2 gd1 gd0 v dd 1 bd3 bd2 bd1 bd0 bl k hftot v ss 1 rout gout bout rref v dd 2 ccomp v ss 2 100 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 26 25 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 51 50 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 lc74736pt top view
lc74736pt no.a0569-5/106 pin functions pin no. symbol type functional description 1 v ss 1 ground connect a ground to this pin. (digital system ground) 2 v dd 1 power supply (+3.3v) digital system power supply: +3.3v 3 oscin 4 oscout lc oscillator connect to the character output dot clock generator oscillator coil and capacitor. 5 extclk external clock signal input receives an external clock signal. capacitor coupling, 50% duty cycle, 0.5vp-p or higher 6 ctrl1 oscin oscillator input control switches between exte rnal clock input mode and lc oscillator mode. low: lc oscillator, high: external clock input more+ or control with more+ command 7 sclk clock input clock input for the serial data input system more+ (this input has hysteresis characteristics.) 8 sin data input serial data input more+ (this input has hysteresis characteristics.) 9 cs enable input enable input for the serial data input system. serial data input is enabled when this pin is set low. more+ (this input has hysteresis characteristics.) 10 vsync vertical sync signal input vertical sync signal input more+ (this input has hysteresis characteristics.) 11 hsync horizontal sync signal input horizontal sync signal input more+ (this input has hysteresis characteristics.) 12 test1 test mode contro l 1 test mode control 1 low: normal operation, high: test mode more+ 13 test2 test mode contro l 2 test mode control 2 low: normal operation, high: test mode (scan mode) more+ 14 rst reset input system reset input more+ (this input has hysteresis characteristics.) 15 clkout clock output clock output 16 v ss 1 ground connect a ground to this pin. (digital system ground) 17 nc 18 nc 19 nc 20 nc 21 nc 22 v ss 4 ground connect a ground tro this pin. (pll system power supply) 23 pd0 pll charge pump output pll vco control voltage input charge pump output connect a lpf (lug lead filter) to this pin. voltage input for internal vco control 24 vcor vco variable range adjustment used to adj ust variable voltage range of internal vco. connect a resistor to this pin. 25 v dd 4 power supply (+3.3v) pll system power supply: +3.3v 26 bfin amplifier input oscilla tion input for external vco 27 bfout amplifier output osc illation output for external vco 28 rd3 rout output: bit 3 29 rd2 rout output: bit 2 30 rd1 rout output: bit 1 31 rd0 rout output: bit 0 rout output this is a 4-bit digital output with values from 0000 to 1111. 32 gd3 gout output: bit 3 33 gd2 gout output: bit 2 34 gd1 gout output: bit 1 35 gd0 gout output: bit 0 gout output this is a 4-bit digital output with values from 0000 to 1111. 36 v dd 1 power supply (+3.3v) digital system power supply: +3.3v continued on next page.
lc74736pt no.a0569-6/106 continued from preceding page. pin no. symbol type functional description 37 bd3 bout output: bit 3 38 bd2 bout output: bit 2 39 bd1 bout output: bit 1 40 bd0 bout output: bit 0 bout output this is a 4-bit digital output with values from 0000 to 1111. 41 blk blanking signal output this signal indicates the osd display period. 42 hftot halftone control signal output osd halftone period control signal synthesized in the next stage ic. 43 v ss 1 ground connect a ground to this pin. (digital system ground) 44 rout rout output: analog d/a converter (4 bits ) output. connect a resistor ro to this pin. 45 gout gout output: analog d/a converter (4 bits) output. connect a resistor ro to this pin. 46 bout bout output: analog d/a converter (4 bits) output. connect a resistor ro to this pin. 47 rref reference resistor connection connect a reference register to this pin. 48 v dd 2 power supply (+3.3v) d/a c onverter power supply: +3.3v 49 ccomp phase correction capacitor co nnection capacitor connection: 1.5 f 50 v ss 2 ground connect a ground to this pin. (d/a converter ground) 51 d15 data input 15 rom data input 15. more+ [msb] 52 d14 data input 14 rom data input 14. more+ 53 d13 data input 13 rom data input 13. more+ 54 d12 data input 12 rom data input 12. more+ 55 d11 data input 11 rom data input 11. more+ [msb] 56 d10 data input 10 rom data input 10. more+ 57 d9 data input 9 rom data input 9. more+ 58 d8 data input 8 rom data input 8. more+ 59 v ss 1 ground connect a ground to this pin. (digital system ground) 60 v dd 1 power supply (+3.3v) digital system power supply: +3.3v 61 d7 data input 7 rom data input 7. more+ 62 d6 data input 6 rom data input 6. more+ 63 d5 data input 5 rom data input 5. more+ 64 d4 data input 4 rom data input 4. more+ 65 d3 data input 3 rom data input 3. more+ 66 d2 data input 2 rom data input 2. more+ 67 d1 data input 1 rom data input 1. more+ 68 d0 data input 0 rom data input 0. more+ [lsb][lsb] 69 v ss 1 ground connect a ground to this pin. (digital system ground) 70 v dd 1 power supply (+3.3v) power supply: (+3.3v: digital system) 71 v ss 3 ground connect a ground to this pin. (external rom output system ground) 72 v dd 3 power supply (+3.3 or +5.5v) power supply (external rom output system power supply) 73 oe output enable rom output enable output. this is an active low output. 74 ce chip enable rom chip enable output. this is an active low output. 75 a19 address output 19 rom address output 19 76 a18 address output 18 rom address output 18 77 a17 address output 17 rom address output 17 78 a16 address output 16 rom address output 16 79 v ss 3 ground connect a ground to this pin. (external rom output system ground) 80 v dd 3 power supply (+3.3 or +5.5v) power supply (external rom output system power supply) 81 a15 address output 15 rom address output 15 82 a14 address output 14 rom address output 14 83 a13 address output 13 rom address output 13 84 a12 address output 12 rom address output 12 85 a11 address output 11 rom address output 11 continued on next page.
lc74736pt no.a0569-7/106 continued from preceding page. pin no. symbol type functional description 86 a10 address output 10 rom address output 10 87 a9 address output 9 rom address output 9 88 a8 address output 8 rom address output 8 89 v ss 3 ground connect a ground to this pin. (external rom output system ground) 90 v dd 3 power supply (+3.3 or +5.5v) power supply (external rom output system power supply) 91 a7 address output 7 rom address output 7 92 a6 address output 6 rom address output 6 93 a5 address output 5 rom address output 5 94 a4 address output 4 rom address output 4 95 a3 address output 3 rom address output 3 96 a2 address output 2 rom address output 2 97 a1 address output 1 rom address output 1 98 a0 address output 0 rom address output 0 99 v ss 3 ground connect a ground to this pin. (external rom output system ground) 100 v dd 3 power supply (+3.3 or +5.5v) power supply (external rom output system power supply) specifications absolute maximum ratings at ta=25 c parameter symbol conditions ratings unit v dd 1 v dd 1,v dd 2, and v dd 4 v ss -0.3 to v ss +4.6 v supply voltage v dd 3 v dd 3 v ss -0.3 to v ss +6.0 v input voltage v in all input pins v ss -0.3 to v dd 1+0.3 v v out 1 rd3 to rd0, gd3 to gd0, bd3 to bd0, blk, hftot outputs v ss -0.3 to v dd 1+0.3 v output voltage v out 2 a0 to 19, ce , oe outputs v ss -0.3 to v dd 3+0.3 v maximum power dissipation pd max 275 mw operating temperature topr -40 to +85 c storage temperature tstg -40 to +125 c recommended operating conditions ratings parameter symbol conditions min typ max unit v dd 1 v dd 1, 2, and v dd 4 3.0 3.3 3.6 v supply voltage v dd 3 v dd 3 3.0 3.3 5.5 v v ih 1 ctrl1, test1, test2 0.7v dd 1 5.5v v ih 2 sclk, sin, cs , vsync, hsync, rst 0.8v dd 1 5.5v input high-level voltage v ih 3 d0 to d15 0.7v dd 1 5.5v v il 1 ctrl1, test1, test2 v ss -0.3 0.3v dd 1v v il 2 sclk, sin, cs , vsync, hsync, rst v ss -0.3 0.2v dd 1v input low-level voltage v ih 3 d0 to d11 v ss -0.3 0.3v dd 1v oscillator frequency (lc) fosc1 oscin and oscout oscillator pins (lc oscillator) 10 mhz fosc2 oscin, v dd 1 = 3.3v 33 40 mhz external clock input v in 1 v dd 1 = 3.3v ctrl1 = high 0.5 3.3 vp-p oscillator frequency (vco) fosc3 vco oscillator (internal) 7 40mhz vrefda reference voltage 1.1 v rfda output load resistance rout, gout, bout 120 225 d/a converter (4-bit, 3 ch) when maximum output voltage = 0.7v rref reference load resistance, rref 1100
lc74736pt no.a0569-8/106 electrical characteristics at ta = -40 to +85 c, v dd = 3.3v unless otherwise specified ratings parameter symbol pin conditions min typ max unit v oh 1 rd3 to rd0, gd3 to gd0, bd3 to bd0, blk, and hftot outputs v dd 1 = 3.0v i oh 1 = -8ma v dd 1 -0.8 v v oh 2 a0 to a19, ce , and oe v dd 3 = 3.0v i oh 2 = -8ma v dd 3 -0.8 v output high-level voltage voh3 a0 to a19, ce , and oe v dd 3 = 4.5v i oh 3 = -8ma v dd 3 -0.8 v v ol 1 rd3 to rd0, gd3 to gd0, bd3 to bd0, blk, and hftot outputs v dd 1 = 3.0v i ol 1 = 8ma 0.4 v v ol 2 a0 to a19, ce , and oe v dd 3 = 3.0v i ol 2 = 8ma 0.4 v output low-level voltage v ol 3 a0 to a19, ce , and oe v dd 3 = 4.5v i ol 3 = 8ma 0.4 v i ih 1 ctrl1, test1, test2 sclk, sin, cs , vsync, hsync, rst v in = v dd 1 10 a i ih 2 d0 to d15 v in = v dd 3 10 a i il 1 ctrl1, test1, test2 sclk, sin, cs , vsync, hsync v in = v ss -10 a input current i il 2 d0 to d15 v in = v ss -10 a i dd 1 v dd 1 all outputs open oscin: 20mhz 25 ma i dd 2 v dd 2 d/a on 22 ma i dd 3 v dd 3 10 ma operating current drain i dd 4 v dd 4 vco on 22 ma clk clock frequency 20 mhz v max maximum output voltage v dd 2 = 3.3v 0.25 1.5 v d/a converter v min0 minimum output voltage v dd 2 = 3.3v 0 v timing characteristics osd write (see figure 1.) at ta = -40 to +85c, v dd 1 = 3.3v 0.3v ratings parameter symbol conditions min typ max unit t w (sclk) sclk 200 ns minimum input pulse width t w (cs) cs (the period cs is high) 1 s t su (cs) cs 200 ns data setup time t su (sin) sin 200 ns t h (cs) cs 2 s data hold time t h (sin) sin 200 ns t word the time to write 8 bits of data 4.2 s one word write time t wt ram data write time 1 s
lc74736pt no.a0569-9/106 supplementary materials figure 1 osd serial data input timing t su (cs) t w (cs) t w (sclk) t w (sclk) t su (sin) t word t h (sin) t h (cs) sclk sin cs sclk t wt cs 0 1 5 6 7 0 1 4 5 6 7
lc74736pt no.a0569-10/106 system block diagram v ss 1 to 4 cs v dd 1 to 4 vblk vsync hblk hsync rst sclk sin 16-bits latch + command decoder serial-to- parallel converter horizontal direction control register vram fram d/a vco pd cp vcor address control circuit horizontal direction counter vertical direction control register vertical direction counter address control circuit external rom control circuit ram and rom read and write control character size control output control circuit timing generator oscin oscout ctrl1 extclk rd3 to 0 gd3 to 0 bd3 to 0 blk hftot outr oe , ce a 0 to 19 d0 to 15 rout gout bout ccomp cvref rref cpout fc bfin bfout
lc74736pt no.a0569-11/106 display control commands the display control commands have serial input format that consists of 8-bit units tran smitted lsb first. a commands consists of a command identification code in the first byte and data in the second and following bytes. both a first byte and a second byte (16 bits) must be tr ansmitted for each command. commands 10, 11, 12, 6c1, and 701 set the ic to continuous write mode. (continuous write mode is cleared by setting the cs pin high.) display control command table first byte second byte command identification code data data command 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 command00 (write address) main 1: v 1 0 0 0 0 0 0 0 0 0 0 v14 v13 v12 v11 v10 command01 (write address) main 1: h 1 0 0 0 0 0 1 0 0 0 h15 h14 h13 h12 h11 h10 command02 (write address) main 2: v 1 0 0 0 0 1 0 0 0 0 0 v24 v23 v22 v21 v20 command03 (write address) main 2: h 1 0 0 0 0 1 1 0 0 0 h25 h24 h23 h22 h21 h20 command04 (write address) sub 1 0 0 0 1 0 0 0 sv1 sv0 0 0 0 0 sh1 sh0 command10 (character write) main 1 1 0 0 1 0 0 rm2 rm1[1] [2] [3] [4] [5] hf1 hf0 at bxs bxl bxr bxu bxd cb3 cb2 cb1 cb0 cc3 cc2 cc1 cc0 0 ctb1 ctb0 i/e mg1 mg0 ro1 ro0 0 0 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 command11 (character write) main 2 1 0 0 1 0 1 rm2 rm1[1] [2] [3] [4] [5] hf1 hf0 at bxs bxl bxr bxu bxd cb3 cb2 cb1 cb0 cc3 cc2 cc1 cc0 0 ctb1 ctb0 i/e mg1 mg0 ro1 ro0 0 0 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 command12 (character write) sub 1 0 0 1 1 0 rm2 rm1[1] [2] [3] [4] [5] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ctb1 ctb0 i/e mg1 mg0 ro1 ro0 0 0 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 command20 (system control) 1 0 1 0 0 0 0 0 tst tst sys frm ct srm mrm mrm md2 md1 rst ers ers ers er2 ers1 command21 (display control) 1 0 1 0 0 0 0 1 bk bk bk bk dsp dsp dsp dsp 12 02 11 01 bg gs gm2 gm1 command22 (i/o polarity control 1) 1 0 1 0 0 0 1 0 0 blop blo blo blo ckp vip hip 2 1 0 command23 (screen background color) 1 0 1 0 0 0 1 1 dpm dpm bgc bgc bgc bgc bgc bgc hc1 hc0 t1 t0 3 2 1 0 command24 (i/o polarity control 2) 1 0 1 0 0 1 0 0 dpm dpm da sbg gd gd gd ckop md vc sel sl 2 1 0 continued on next page.
lc74736pt no.a0569-12/106 continued from preceding page. first byte second byte command identification code data data command 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 command25 (output control 1) 1 0 1 0 0 1 0 1 ceh tok vi lcs otm otm lcs lcs sl sl psl sp2 1 0 stp off command26 (output control 2) 1 0 1 0 0 1 1 0 hf tbl kbl bl bl otm rot dot off off 2 1 0 2 off off command27 (output control 3) 1 0 1 0 0 1 1 1 0 hft hft hft tok tok tok tok 2 1 0 cb4 cb3 cb2 cb1 command28 (output control 4) 1 0 1 0 1 0 0 0 hpg hps hpm hpm vpg vps vpm vpm 9 9 29 19 8 8 28 18 command29 (output control 5) 1 0 1 0 1 0 0 1 0 svh svh shh shh 0 0 ml 1 0 1 0 ch command2a (display area control 1) 1 0 1 0 1 0 1 0 0 hin hi hi vi vi 0 0 din d1 d0 d1 d0 command30 (vertical display start position: main 1) 1 0 1 1 0 0 0 0 vpm vpm vpm vpm vpm vpm vpm vpm 17 16 15 14 1 12 11 10 command31 ( horizontal display start position: main 1 ) 1 0 1 1 0 0 1 hpm 18 hpm hpm hpm hpm hpm hpm hpm hpm 17 16 15 14 13 12 11 10 command32 (vertical display start position: main 2) 1 0 1 1 0 1 0 0 vpm vpm vpm vpm vpm vpm vpm vpm 27 26 25 24 23 22 21 20 command33 ( horizontal display start position: main 2 ) 1 0 1 1 0 1 1 hpm 28 hpm hpm hpm hpm hpm hpm hpm hpm 27 26 25 24 23 22 21 20 command34 (vertical display start positions: sub) 1 0 1 1 1 0 0 0 vps vps vps vps vps vps vps vps 7 6 5 4 3 2 1 0 command35 (horizontal display start position: sub) 1 0 1 1 1 0 1 hps 8 hps hps hps hps hps hps hps hps 7 6 5 4 3 2 1 0 command36 (vertical display start positions: screen) 1 0 1 1 1 1 0 0 vpg vpg vpg vpg vpg vpg vpg vpg 7 6 5 4 3 2 1 0 command37 ( horizontal display start position: screen ) 1 0 1 1 1 1 1 hpg 8 hpg hpg hpg hpg hpg hpg hpg hpg 7 6 5 4 3 2 1 0 continued on next page.
lc74736pt no.a0569-13/106 continued from preceding page. first byte second byte command identification code data data command 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 command40 (character size control) 1 1 0 0 0 0 0 0 0 0 0 0 szv1 szv0 szh1 szh0 command41 main 1 (character size control: line setting u) 1 1 0 0 0 0 0 1 lsz lsz lsz lsz lsz lsz lsz lsz 7 6 5 4 3 2 1 0 command42 main 1 (character size control: line setting d) 1 1 0 0 0 0 1 0 lsz lsz lsz lsz lsz lsz lsz lsz 15 14 13 12 11 10 9 8 command43 main 1 (character size control: line setting d2) 1 1 0 0 0 0 1 1 0 0 0 0 0 0 lsz lsz 17 16 command44 main 2 (character size control: line setting u) 1 1 0 0 0 1 0 0 lsz lsz lsz lsz lsz lsz lsz lsz 7 6 5 4 3 2 1 0 command45 main 2 (character size control: line setting d) 1 1 0 0 0 1 0 1 lsz lsz lsz lsz lsz lsz lsz lsz 15 14 13 12 11 10 9 8 command46 main 2 (character size control: line setting d2) 1 1 0 0 0 1 1 0 0 0 0 0 0 0 lsz lsz 17 16 command50 (box control u) 1 1 0 1 0 0 0 0 bxl bxl bxu bxu bxu bxu bxu bxu w1 w0 ct1 ct0 c3 c2 c1 c0 command51 (box control d) 1 1 0 1 0 0 0 1 bxr bxr bxd bxd bxd bxd bxd bxd w1 w0 ct1 ct0 c3 c2 c1 c0 command52 main 1 (box control: line setting u) 1 1 0 1 0 0 1 0 lbx lbx lbx lbx lbx lbx lbx lbx 7 6 5 4 3 2 1 0 command53 main 1 (box control: line setting d) 1 1 0 1 0 0 1 1 lbx lbx lbx lbx lbx lbx lbx lbx 15 14 13 12 11 10 9 8 command54 main 1 (box control: line setting d2) 1 1 0 1 0 1 0 0 0 0 0 0 0 0 lbx lbx 17 16 command55 main 2 (box control: line setting u) 1 1 0 1 0 1 0 1 lbx lbx lbx lbx lbx lbx lbx lbx 7 6 5 4 3 2 1 0 command56 main 2 (box control: line setting d) 1 1 0 1 0 1 1 0 lbx lbx lbx lbx lbx lbx lbx lbx 15 14 13 12 11 10 9 8 command57 main 2 (box control: line setting d2) 1 1 0 1 0 1 1 1 0 0 0 0 0 0 lbx lbx 17 16 continued on next page.
lc74736pt no.a0569-14/106 continued from preceding page. first byte second byte command identification code data data command 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 command58 (line spacing control 1) 1 1 0 1 1 0 0 0 0 gyb gs gs gy gy gy gy ck 1 0 3 2 1 0 command59 (line spacing control 2) 1 1 0 1 1 0 0 1 bxd bxu gyh bxh fch bxc bxc bxc w w sl sl sl 3 2 1 command5a main 1 (line spacing control: line setting u) 1 1 0 1 1 0 1 0 lgy lgy lgy lgy lgy lgy lgy lgy 7 6 5 4 3 2 1 0 command5b main 1 (line spacing control: line setting u) 1 1 0 1 1 0 1 1 lgy lgy lgy lgy lgy lgy lgy lgy 15 14 13 12 11 10 9 8 command5c main 1 (line spacing control: line setting d2) 1 1 0 1 1 1 0 0 0 0 0 0 0 0 lgy lgy 17 16 command5d main 2 (line spacing control: line setting u) 1 1 0 1 1 1 0 1 lgy lgy lgy lgy lgy lgy lgy lgy 7 6 5 4 3 2 1 0 command5e main 2 (line spacing control: line setting d) 1 1 0 1 1 1 1 0 lgy lgy lgy lgy lgy lgy lgy lgy 15 14 13 12 11 10 9 8 command5f main 2 (line spacing control: line setting d2) 1 1 0 1 1 1 1 1 0 0 0 0 0 0 lgy lgy 17 16 command60 (border control) 1 1 1 0 0 0 0 0 blk blk egc egc egc egc egc egc t1 t0 3 2 1 0 command61 main 1 (border control: line setting u) 1 1 1 0 0 0 0 1 lfc lfc lfc lfc lfc lfc lfc lfc 7 6 5 4 3 2 1 0 command62 main 1 (border control: line setting d) 1 1 1 0 0 0 1 0 lfc lfc lfc lfc lfc lfc lfc lfc 15 14 13 12 11 10 9 8 command63 main 1 (border control: line setting d2) 1 1 1 0 0 0 1 1 0 0 0 0 0 0 lfc lfc 17 16 command64 main 2 (border control: line setting u) 1 1 1 0 0 1 0 0 lfc lfc lfc lfc lfc lfc lfc lfc 7 6 5 4 3 2 1 0 command65 main 2 (border control: line setting d) 1 1 1 0 0 1 0 1 lfc lfc lfc lfc lfc lfc lfc lfc 15 14 13 12 11 10 9 8 command66 main 2 (border control: line setting d2) 1 1 1 0 0 1 1 0 0 0 0 0 0 0 lfc lfc 17 16 command67 (pll control 1) 1 1 1 0 0 1 1 1 evo lc eck vco vcs vcs cksl cksl off off off off 1 0 1 0 command68 (pll control 2) 1 1 1 0 1 0 0 0 0 0 0 div div div div div 12 11 10 9 8 command69 (pll control 3) 1 1 1 0 1 0 0 1 div div div div div div div div 7 6 5 4 3 2 1 0 command6a (pll control 5) 1 1 1 0 1 0 1 0 0 hd dz dz hr did did did sl 1 0 sl 2 1 0 command6c0 (write address) color table 1 1 1 0 1 1 0 0 0 0 ctn ctn cta cta cta cta 1 0 3 2 1 0 command6c1 (data write) color table 1 1 1 0 1 1 1 rm3[1] [2] 0 0 hft tok tb3 tb2 tb1 tb0 tg3 tg2 tg1 tg0 tr3 tr2 tr1 tr0 continued on next page.
lc74736pt no.a0569-15/106 continued from preceding page. first byte second byte command identification code data data command 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 command700 (character ram1) writeaddress 1 1 1 1 0 0 0 0 fad fad frn frn fva fva fva fva 1 0 1 0 3 2 1 0 command701 (character ram2) write 1 1 1 1 0 0 1 rm3[1] [2] d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 command710 (wvga rom) 1 1 1 1 0 1 0 0 0 0 cko cko wfc wra wra wra s1 s0 md m2 m1 m0 command711 (pll control 6) 1 1 1 1 0 1 0 1 rstb 0 vcrs vcrs cp 0 cp cp 1 0 x2 i11 i0 command712 (pll control 7) 1 1 1 1 0 1 1 0 0 stb res scp div gan gan gan cp cp cp ecp 2 1 0 1 command00 (main screen 1: horizon tal write address setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 0 5 - 0 4 - 0 command 0 identification code main screen 1 memory horizontal write address setting 3 - 0 2 - 0 1 - 0 sub-identification code: 0 0 - 0 (2) second byte content da0 to 7 register state function notes 7 - 0 6 - 0 5 - 0 0 4 v14 [msb] 1 0 3 v13 1 0 2 v12 1 0 1 v11 1 0 0 v10 [lsb] 1 main screen 1 memory line address (0 to 11, hexadecimal) 15 lines: 0e (hexadecimal) 18 lines: 11 (hexadecimal) com24-2: line number specification *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-16/106 2 command01 (main screen 1: vertical write address setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 0 5 - 0 4 - 0 command 0 identification code main screen 1 memory vert ical write address setting 3 - 0 2 - 0 1 - 1 sub-identification code: 1 0 - 0 (2) second byte content da0 to 7 register state function notes 7 - 0 6 - 0 5 - 0 0 4 h15 [msb] 1 0 4 h14 1 0 3 h13 1 0 2 h12 1 0 1 h11 1 0 0 h10 [lsb] 1 main screen 1 memory character position address (0 to 21, hexadecimal) 30 characters: 1d (hexadecimal) 33 characters: 20 (hexadecimal) 34 characters: 21 (hexadecimal) com23-2: character number specification *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-17/106 3 command02 (main screen 2: horizon tal write address setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 0 5 - 0 4 - 0 command 0 identification code main screen 2 memory horizontal write address setting 3 - 0 2 - 1 1 - 0 sub-identification code: 2 0 - 0 (2) second byte content da0 to 7 register state function notes 7 - 0 6 - 0 5 - 0 0 4 v24 [msb] 1 0 3 v23 1 0 2 v22 1 0 1 v21 1 0 0 v20 [lsb] 1 main screen 2 memory line address (0 to 0e, hexadecimal) 15 lines: 0e (hexadecimal) 18 lines: 11 (hexadecimal) com24-2: line number specification *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-18/106 4 command03 (main screen 2: vertical write address setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 0 5 - 0 4 - 0 command 0 identification code main screen 2 memory vert ical write address setting 3 - 0 2 - 1 1 - 1 sub-identification code: 3 0 - 0 (2) second byte content da0 to 7 register state function notes 7 - 0 6 - 0 5 - 0 0 4 h25 [msb] 1 0 4 h24 1 0 3 h23 1 0 2 h22 1 0 1 h21 1 0 0 h20 [lsb] 1 main screen 2 memory character position address (0 to 21, hexadecimal) 30 characters: 1d (hexadecimal) 33 characters: 20 (hexadecimal) 34 characters: 21 (hexadecimal) com23-3: character number specification *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-19/106 5 command04 (subscreen write address setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 0 5 - 0 4 - 0 command 0 identification code subscreen write address setting 3 - 1 2 - 0 1 - 0 sub-identification code: 4 0 - 0 (2) second byte content da0 to 7 register state function notes 0 7 sv1 1 0 6 sv0 1 subscreen memory line address 0 to 3 (hexadecimal) 4 lines (maximum) com29-2: line number specification 5 - 0 4 - 0 3 - 0 2 - 0 0 1 sh1 1 0 0 sh0 1 subscreen memory character position address 0 to 3 (hexadecimal) 4 characters (maximum) com29-2: character number specification *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-20/106 6 command10 (main screen 1 display character data write setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 0 5 - 0 4 - 1 command 1 identification code display character data write setting when this command has been issued, the ic remains in display character data write mode until the cs pin is set high. 3 - 0 2 - 0 sub-identification code: 0 0 1 rm2 1 0 0 rm1 1 rm2 rm1 mode 0 0 [1][2][3][4][5] end 0 1 [1][2][3][4][5] continuous 1 0 [3][4][5] continuous 1 1 [2][3][4][5] continuous continuous write mode selection (2) second byte-[1] content da0 to 7 register state function notes 0 7 hft1 1 0 6 hft0 1 hft1 hft0 0 0 none 0 1 character only 1 0 character background only 1 1 character+character background halftone specification graphic is processed as a character. com59-2 0 blinking off 5 at 1 blinking on blinking specification 0 raised 4 bxs 1 recessed box specification: raised/recessed 0 none 3 bxl 1 box displayed box specification: left side 0 none 2 bxr 1 box displayed box specification: right side 0 none 1 bxu 1 box displayed box specification: upper 0 none 0 bxd 1 box displayed box specification: down *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-21/106 (3) second byte-[2] content da0 to 7 register state function notes 0 7 cb3 [msb] 1 0 6 cb2 1 0 5 cb1 1 0 4 cb0 [lsb] 1 character background color specification 0000 to 1111, or 0 to f (hexadecimal) character background color specification when a character glyph is specified, 1 of 16 colors may be selected. 0 3 cc3 [msb] 1 0 2 cc2 1 0 1 cc1 1 0 0 cc0 [lsb] 1 character color specification 0000 to 1111, or 0 to f (hexadecimal) character color specification when a character glyph is specified, 1 of 16 colors may be selected. (4) second byte-[3] content da0 to 7 register state function notes 7 - 0 0 6 ctb1 1 0 5 ctb0 1 ctb1 ctb0 0 0 color table number 1 0 1 color table number 2 1 0 color table number 3 1 1 color table number 4 color table selection 0 character ram (internal) 4 i/e 1 external rom rom selection 0 3 m/g1 1 0 1 2 m/g0 1 mg1 mg0 0 0 character 0 1 graphic 1(cb, cc invalid) 1 0 graphic 2 ctb address shown with cb chantged to ctb address shown with cc 1 1 graphic 3 ctbno of address shown with cb changed to ctbno shown with cc1, cc0 character/graphic specification 0 1 rom1 1 0 0 rom0 1 rom1 rom0 0 0 rom area number 1 0 1 rom area number 2 1 0 rom area number 3 1 1 rom area number 4 rom area selection *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-22/106 (5) second byte-[4] content da0 to 7 register state function notes 7 - 0 6 - 0 0 5 c13 [msb] 1 0 4 c12 1 0 3 c11 1 0 2 c10 1 0 1 c9 1 0 0 c8 1 character code specification (6) second byte-[5] content da0 to 7 register state function notes 0 7 c7 1 0 6 c6 1 0 5 c5 1 0 4 c4 1 0 3 c3 1 0 2 c2 1 0 1 c1 1 0 0 c0 [lsb] 1 character code external rom: 16384 characters 0000 to 3fff (hexadecimal) 0 to 16383 character ram (internal): qvga mode: 0 to 3, hexadecimal, 4 characters wvga mode: 0 hexadecimal, 1 character * transparent character specification i/e = 0 (internal character ram) m/g10 = 00 (character) code = ff (hexadecimal) character code specification *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-23/106 7 command11 (main screen 2 display character data write setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 0 5 - 0 4 - 1 command 1 identification code display character data write setting when this command has been issued, the ic remains in display character data write mode until the cs pin is set high. 3 - 0 2 - 0 sub-identification code: 1 0 1 rm2 1 0 0 rm1 1 rm2 rm1 mode 0 0 [1][2][3][4][5] end 0 1 [1][2][3][4][5] continuous 1 0 [3][4][5] continuous 1 1 [2][3][4][5] continuous continuous write mode selection (2) second byte-[1] content da0 to 7 register state function notes 0 7 hft1 1 0 6 hft0 1 hft1 hft0 0 0 none 0 1 character only 1 0 character background only 1 1 character+character background halftone specification graphic is processed as a character. com59-2 0 blinking off 5 at 1 blinking on blinking specification 0 raised 4 bxs 1 recessed box specification: raised/recessed 0 none 3 bxl 1 box displayed box specification: left side 0 none 2 bxr 1 box displayed box specification: right side 0 none 1 bxu 1 box displayed box specification: upper 0 none 0 bxd 1 box displayed box specification: down *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-24/106 (3) second byte-[2] content da0 to 7 register state function notes 0 7 cb3 [msb] 1 0 6 cb2 1 0 5 cb1 1 0 4 cb0 [lsb] 1 character background color specification 0000 to 1111, or 0 to f (hexadecimal) character background color specification when a character glyph is specified, 1 of 16 colors may be selected. 0 3 cc3 [msb] 1 0 2 cc2 1 0 1 cc1 1 0 0 cc0 [lsb] 1 character color specification 0000 to 1111, or 0 to f (hexadecimal) character color specification when a character glyph is specified, 1 of 16 colors may be selected. (4) second byte-[3] content da0 to 7 register state function notes 7 - 0 0 6 ctb1 1 0 5 ctb0 1 ctb1 ctb0 0 0 color table number 1 0 1 color table number 2 1 0 color table number 3 1 1 color table number 4 color table selection 0 character ram (internal) 4 i/e 1 external rom rom selection 0 3 m/g1 1 0 1 2 m/g0 1 mg1 mg0 0 0 character 0 1 graphic 1 (cb, cc invalid) 1 0 graphic 2 ctb address shown with cb changed to ctb address shown with cc. 1 1 graphic 3 ctbno of address shown with cb. changed to ctbno shown with cc1, cc0. character/graphic specification 0 1 rom1 1 0 0 rom0 1 rom1 rom0 0 0 rom area number 1 0 1 rom area number 2 1 0 rom area number 3 1 1 rom area number 4 rom area selection *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-25/106 (5) second byte-[4] content da0 to 7 register state function notes 7 - 0 6 - 0 0 5 c13 [msb] 1 0 4 c12 1 0 3 c11 1 0 2 c10 1 0 1 c9 1 0 0 c8 1 character code specification (6) second byte-[5] content da0 to 7 register state function notes 0 7 c7 1 0 6 c6 1 0 5 c5 1 0 4 c4 1 0 3 c3 1 0 2 c2 1 0 1 c1 1 0 0 c0 [lsb] 1 character code external rom: 16384 characters 0000 to 3fff (hexadecimal) 0 to 16383 character ram (internal): qvga mode: 0 to 3, hexadecimal, 4 characters wvga mode: 0 hexadecimal, 1 character * transparent character specification i/e = 0 (internal character ram) m/g10 = 00 (character) code = ff (hexadecimal) character code specification *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-26/106 12 command12 (subscreen display character data write setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 0 5 - 0 4 - 1 command 1 identification code display character data write setting when this command has been issued, the ic remains in display character data write mode until the cs pin is set high. 3 - 1 2 - 0 sub-identification code 2 0 1 rm2 1 0 0 rm1 1 rm2 rm1 mode 0 0 [1][2][3][4][5] end 0 1 [1][2][3][4][5] continuous 1 0 [3][4][5] continuous 1 1 [2][3][4][5] continuous continuous write mode selection (2) second byte-[1] content da0 to 7 register state function notes 7 - 0 6 - 0 5 - 0 4 - 0 3 - 0 2 - 0 1 - 0 0 - 0 (3) second byte-[2] content da0 to 7 register state function notes 7 - 0 6 - 0 5 - 0 4 - 0 3 - 0 2 - 0 1 - 0 0 - 0 *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-27/106 (4) second byte-[3] content da0 to 7 register state function notes 7 - 0 0 6 ctb1 1 0 5 ctb0 1 ctb1 ctb0 0 0 color table number 1 0 1 color table number 2 1 0 color table number 3 1 1 color table number 4 color table selection 0 character ram (internal) 4 i/e 1 external rom rom selection 0 3 m/g1 1 0 1 2 m/g0 1 mg1 mg0 0 0 character (only when transparent character is specified.) 0 1 graphic 1 only graphic only 1 - 0 0 - 0 (5) second byte-[4] content da0 to 7 register state function notes 7 - 0 6 - 0 0 5 c13 [msb] 1 0 4 c12 1 0 3 c11 1 0 2 c10 1 0 1 c9 1 0 0 c8 1 character code specification *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-28/106 (6) second byte-[5] content da0 to 7 register state function notes 0 7 c7 1 0 6 c6 1 0 5 c5 1 0 4 c4 1 0 3 c3 1 0 2 c2 1 0 1 c1 1 0 0 c0 [lsb] 1 character code external rom: 16384 characters 0000 to 3fff (hexadecimal) 0 to 16383 character ram (internal): qvga mode: 0 to 3, hexadecimal, 4 characters wvga mode: 0 hexadecimal, 1 character * transparent character specification i/e = 0 (internal character ram) m/g10 = 00 (character) code = ff (hexadecimal) character code specification *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-29/106 9 command20 (system control setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 0 5 - 1 4 - 0 command 2 identification code system control settings 3 - 0 2 - 0 1 - 0 0 - 0 sub-identification code 0 (2) second byte content da0 to 7 register state function notes 0 normal operation 7 tst md2 1 test mode 2 do not use test mode. this bit must always be set to 0. 0 normal operation 6 tst md1 1 test mode 1 do not use test mode. this bit must always be set to 0. 0 5 sys rst 1 reset all registers (all bits set to 0.) the registers are reset when the cs pin is low. the reset state is cleared when the cs pin goes high. 0 4 frm ers 1 erase fontram (sets all values to 00.) applications must provide a wait time of about 1ms. use dspoff to execute this operation. 0 3 ct ers 1 erase the color table. (sets all values to 00.) applications must provide a wait time of about 1ms. use dspoff to execute this operation. 0 2 srm ers 1 erase sub-ram. (sets all values to 00.) wallpaper applications must provide a wait time of about 1ms. use dspoff to execute this operation. 0 1 mrm er2 1 erase main ram. (sets all values to 00.) main screen applications must provide a wait time of about 1ms. use dspoff to execute this operation. 0 0 mrm er1 1 erase main ram. (sets all values to 00.) main screen applications must provide a wait time of about 1ms. use dspoff to execute this operation. *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-30/106 10 command21 (display control setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 0 5 - 1 4 - 0 command 2 identification code display control 3 - 0 2 - 0 1 - 0 0 - 1 extended command 1 identification code (2) second byte content da0 to 7 register state function notes 0 7 bk12 1 0 6 bk02 1 bk12 bk02 blinking period 0 0 1/16 0 1 1/32 1 0 1/64 blinking period main 2 specified for screen units. 0 5 bk11 1 0 4 bk01 1 bk11 bk01 blinking period 0 0 1/16 0 1 1/32 1 0 1/64 blinking period main 1 specified for screen units. 0 display off 3 dsp bg 1 display on screen background color 0 display off 2 dsp gs 1 display on subscreen (wallpaper) 0 display off 1 dsp gm2 1 display on main screen 2 0 display off 0 dsp gm1 1 display on main screen 1 *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-31/106 11 command22 (i/o polarity control 1 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 0 5 - 1 4 - 0 command 2 identification code i/o polarity control 1 3 - 0 2 - 0 1 - 1 0 - 0 extended command 2 identification code (2) second byte content da0 to 7 register state function notes 7 - 0 0 blk output: positive polarity 6 blop 1 blk output: negative polarity blk output polarity selection 5 blo2 0 0 4 blo1 1 0 3 blo0 1 blo210 blk output 0 0 0 normal character.+charcter background+graphic 0 0 1 character only 0 1 0 character background only 0 1 1 graphic only 1 0 0 character+character background only 1 0 1 character+graphic only 1 1 0 character background+graphic only blk output control character, character background, and graphic output control. border specification is enabled when character background output is selected. 0 clock input: positive polarity 2 ckp 1 clock input: negative polarity clock input polarity selection 0 vsync input: negative polarity 1 vip 1 vsync input: positive polarity vsync input polarity selection 0 hsync input: negative polarity 0 hip 1 hsync input: positive polarity hsync input polarity selection *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-32/106 12 command23 (screen background color setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 0 5 - 1 4 - 0 command 2 identification code screen background color 3 - 0 2 - 0 1 - 1 0 - 1 extended command 3 identification code (2) second byte content da0 to 7 register state function notes 0 7 dpm hc1 1 0 6 dpm hc0 1 hc1 0 characters 0 0 30 characters (1d, hexadecimal) 0 1 33 characters (20, hexadecimal) 1 0 34 characters (21, hexadecimal) main screen display area specification horizontal direction 0 5 bgc t1 1 0 4 bgc t0 1 t1 t0 color table setting 0 0 color table number 1 0 1 color table number 2 1 0 color table number 3 1 1 color table number 4 screen background color color table setting 0 3 bgc3 1 0 2 bgc2 1 0 1 bgc1 1 0 0 bgc0 1 screen background color 0000 to 1111 0 to f (hexadecimal) screen background color setting 1 of 16 colors may be selected. *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-33/106 13 command24 (i/o polarity control 2 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 0 5 - 1 4 - 0 command 2 identification code i/o polarity control 2 3 - 0 2 - 1 1 - 0 0 - 0 extended command 4 identification code (2) second byte content da0 to 7 register state function notes 0 qvga mode (16 16 dots) 7 dpm md 1 wvga mode (24 32 dots) display mode selection 0 15 lines 6 dpm vc 1 18 lines mmain screen display area specification vertical 0 d/a on 5 d/a sel 1 d/a off d/a converter use/no-use selection 0 repeated display (wallpaper) 4 sbg sl 1 cursor display (sprite display) qvga: horizontal 4 characters vertical 4 lines (maximum) wvga: horizontal 2 characters vertical 2 lines (maximum) subscreen display selection com29-2: display area specification 0 3 gd2 1 0 2 gd1 1 0 1 gd0 1 gd2 1 0 screen display [upper lower] 0 0 0 main 1, main 2, wallpaper 0 0 1 main 2, main 1, wallpaper 0 1 0 wallpaper, main 1, main 2 0 1 1 wallpaper, main 2, main 1 1 0 0 main 1, wallpaper, main 2 1 0 1 main 2, wallpaper, main 1 screen display order selection 0 clock output: positive polarity 0 ckop 1 clock output: negative polarity clock output polarity selection *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-34/106 14 command25 (output control 1 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 0 5 - 1 4 - 0 command 2 identification code output control 1 3 - 0 2 - 1 1 - 0 0 - 1 extended command 5 identification code (2) second byte content da0 to 7 register state function notes 0 normal operation 7 cehsl 1 ce pin held fixed at the high level ce pin 0 normal mode 6 toksl 1 transmissive mode the color specified at address 0 in color table no. 1 is displayed in the transmissive state. transparent mode specification specifis effective color table with comn27-2. 0 falling edge detection 5 vipsl 1 rising edge detection selects the detection polarity for the vsync signal. 0 lc oscillator: normal operation (h sync) 4 lcs of2 1 lc oscillator: stop state (off) rstlc also lc oscillator stop control when external clock is input. 0 3 otmd1 1 0 2 otmd0 1 otmd1 otmd0 output 0 0 normal 0 1 disabled 1 0 disabled 1 1 high-impedance state a0 to a19, ce, oe output selection 0 lc oscillator: normal operation (h sync.) 1 lcs stp 1 lc oscillator: always stop state lc oscillator stop control enabled when display is off 0 lc oscillator: normal operation (h sync.) 0 lcs off 1 lc oscillator: stop state (off) lcstop only lc oscillator stop control when external clock is input. *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-35/106 15 command26 (output control 2 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 0 5 - 1 4 - 0 command 2 identification code output control 1 3 - 0 2 - 1 1 - 1 0 - 0 extended command 6 identification code (2) second byte content da0 to 7 register state function notes 0 hftot output on 7 hft off 1 hftot output off=low hftot output setting 0 blk output on 6 blk off 1 blk output off=low blk output setting 0 5 bld2 1 0 4 bld1 1 0 3 bld0 1 bld2 1 0 blk output delay 0 0 0 0 (analog) 0 0 1 +1 0 1 0 +2 0 1 1 -1 (digital) 1 0 0 -2 blk output delay 0 output off=low 2 otm2 1 normal output clkout output output control 0 external rom address, oe, ce output on 1 rot off 1 external rom address, oe, ce output off=low external rom address output setting 0 digital rgb output on 0 dot off 1 digital rgb output off=low digital rgb output setting *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-36/106 16 command27 (output control 3 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 0 5 - 1 4 - 0 command 2 identification code output control 1 3 - 0 2 - 1 1 - 1 0 - 1 extended command 7 identification code (2) second byte content da0 to 7 register state function notes 7 - 0 0 6 hft od2 0 5 hft od1 1 0 4 hft od0 1 hftod2 1 0 0 0 0 0 (analog) 0 0 1 +1 0 1 0 +2 0 1 1 -1 (digital) 1 0 0 -2 hftot output delay 0 address 0000: normal color 3 tok cb4 1 address 0000: transparent color transparent color specification or specifiable color table no. 4 com25-2 enabled by setting toksl to 1. 0 address 0000: normal color 2 tok cb3 1 address 0000: transparent color transparent color specification or specifiable color table no. 3 com25-2 enabled by setting toksl to 1. 0 address 0000: norrmal color 1 tok cb2 1 address 0000: transparent color transparent color specification or specifiable color table no. 2 com25-2 enabled by setting toksl to 1. 0 address 0000: normal color 0 tok cb1 1 address 0000: transparent color transparent color specification or specifiable color table no. 1 com25-2 enabled by setting toksl to 1. *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-37/106 17 command28 (output control 4 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 0 5 - 1 4 - 0 command 2 identification code output control 1 3 - 1 2 - 0 1 - 0 0 - 0 extended command 8 identification code (2) second byte content da0 to 7 register state function notes 0 screen background color h position msb 0 7 hpg 9 1 screen background color h position msb 1 h position screen background color msb 0 subscreen h position msb 0 6 hps 9 1 subscreen h position msb 1 h position subscreen msb 0 main screen 2 h position msb 0 5 hpm2 29 1 main screen 2 h position msb 1 h position main screen 2 msb 0 main screen 1 h position msb 0 4 hpm1 19 1 main screen 1 h position msb 1 h position main screen 1 msb 0 screen background v position msb 0 3 vpg 8 1 screen background v position msb 1 v position screen background color msb 0 subscreen v position msb 0 2 vps 8 1 subscreen v position msb 1 v position subscreen msb 0 main screen 2 v position msb 0 1 vpm2 28 1 main screen 2 v position msb 1 v position main screen 2 msb 0 main screen 1 v position msb 0 0 vpm1 18 1 main screen 1 v position msb 1 v position main screen 1 msb *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-38/106 18 command29 (output control 5 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 0 5 - 1 4 - 0 command 2 identification code output control 1 3 - 1 2 - 0 1 - 0 0 - 1 extended command 9 identification code (2) second byte content da0 to 7 register state function notes 7 - 0 0 6 svh1 1 0 5 svh0 1 svh1 svh0 display area qvga wvga 0 0 1 line - 0 1 2 line - 1 0 3 line 1 line 1 1 4 line 2 line subscreen vertical direction display range selection qvga: 4 lines (maximum) wvga: 2 lines (maximum) 0 4 shh1 1 0 3 shh0 1 shh1 shh0 display area qvga wvga 0 0 1 character - 0 1 2 characters - 1 0 3 characters 1 character 1 1 4 characters 2 characters subscreen horizontal direction display range selection qvga: 4 characters (maximum) wvga: 2 characters (maximum) 2 - 0 1 - 0 0 lsb first 0 ml chg 1 msb first 3-wire control transfer direction selection *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-39/106 18 command2a (display area control 1 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 0 5 - 1 4 - 0 command 2 identification code output control 1 3 - 1 2 - 0 1 - 1 0 - 0 extended command a identification code (2) second byte content da0 to 7 register state function notes 7 - 0 0 normal (lc oscillator control route) 6 hin din 1 direct taking in hsync input selection direct taking-in specification (1) must be used in modes other than lc oscillator. 0 5 hi d1 1 0 4 hi d0 1 hid1 hid0 delay 0 0 0 (initial) 0 1 +1 1 0 +2 1 1 +3 hsync taking in enabled when hindin is set to 1. 0 3 vi d1 1 0 2 vi d0 1 vid1 vid0 delay 0 0 0 (initial) 0 1 +1 1 0 +2 1 1 +3 vsync taking in 1 - 0 0 - 0 *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-40/106 25 command30 (main screen 1: verti cal display start position setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 0 5 - 1 4 - 1 command 3 identification code main screen 1 vertical display start position setting 3 - 0 2 - 0 1 - 0 extended command 0 identification code 0 - 0 (2) second byte content da0 to 7 register state function notes 0 7 vpm17 1 0 6 vpm16 1 0 5 vpm15 1 0 4 vpm14 1 0 3 vpm13 1 0 2 vpm12 1 0 1 vpm11 1 0 0 vpm10 (lsb) 1 the vertical display start position, vsm 1, is given by: 8 vsm1=1h ( 2 n vpm1n) n=0 main screen 1 the vertical display start position is specified by the 9 bits vpm18 to vpm10. the weight of the lsb is 1h. this setting applies in screen units. *: this resistor is set to the all bits zero state when the ic is reset by the rst pin. main screen display area hsm1 vsm1 hsync vsync
lc74736pt no.a0569-41/106 26 command31 (main screen 1: horizonta l display start position setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 0 5 - 1 4 - 1 command 3 identification code main screen: horizontal display start position setting 3 - 0 2 - 0 1 - 1 extended command 1 identification code 0 0 hpm18 1 (2) second byte content da0 to 7 register state function notes 0 7 hpm17 1 0 6 hpm16 1 0 5 hpm15 1 0 4 hpm14 1 0 3 hpm13 1 0 2 hpm12 1 0 1 hpm11 1 0 0 hpm10 (lsb) 1 the horizontal display start position, hsm1, is given by: 9 hsm1=1tc ( 2 n hpm1n)+ n=0 =45tc(qvga) 41tc(wvga) tc: the input clock frequency in operating mode. setting disable range qvga wvga sub h 0 character 00hex 00hex sub h 1 character 00 to 05hex 00 to 15hex (00 to 0chex) sub h 2 characters 00 to 0dhex 00 to 2chex (00 to 1chex) sub h 3 characters 00 to 15hex sub h 4 characters 00 to 1dhex the values in parentheses apply when rom access no. 2 and no. 3 are set. main screen 1 the horizontal display start position is specified by the 10 bits hpm19 to hpm10. the weight of the lsb is 1tc. this setting applies in screen units. *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-42/106 27 command32 (main screen 2: verti cal display start position setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 0 5 - 1 4 - 1 command 3 identification code main screen 2 vertical display start position setting 3 - 0 2 - 1 1 - 0 extended command 2 identification code 0 - 0 (2) second byte content da0 to 7 register state function notes 0 7 vpm27 1 0 6 vpm26 1 0 5 vpm25 1 0 4 vpm24 1 0 3 vpm23 1 0 2 vpm22 1 0 1 vpm21 1 0 0 vpm20 (lsb) 1 the vertical display start position, vsm2, is given by: 8 vsm2=1h ( 2 n vpm2n) n=0 main screen 2 the vertical display start position is specified by the 9 bits vpm28 to vpm20. the weight of the lsb is 1h. this setting applies in screen units. *: this resistor is set to the all bits zero state when the ic is reset by the rst pin. main screen display area hsm2 vsm2 hsync vsync
lc74736pt no.a0569-43/106 28 command33 (main screen 2: horizonta l display start position setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 0 5 - 1 4 - 1 command 3 identification code main screen: horizontal display start position setting 3 - 0 2 - 1 1 - 1 extended command 3 identification code 0 0 hpm28 1 (2) second byte content da0 to 7 register state function notes 0 7 hpm27 1 0 6 hpm26 1 0 5 hpm25 1 0 4 hpm24 1 0 3 hpm23 1 0 2 hpm22 1 0 1 hpm21 1 0 0 hpm20 (lsb) 1 the horizontal display start position, hsm2, is given by: 9 hsm2=1tc ( 2 n hpm2n)+ n=0 =45tc(qvga) 41tc(wvga) tc: the input clock frequency in operating mode. setting disable range qvga wvga sub h 0 character 00hex 00hex sub h 1 character 00 to 05hex 00 to 15hex (00 to 0chex) sub h 2 characters 00 to 0dhex 00 to 2chex (00 to 1chex) sub h 3 characters 00 to 15hex sub h 4 characters 00 to 1dhex the values in parentheses apply when rom access no. 2 and no. 3 are set. main screen 2 the horizontal display start position is specified by the 10 bits hpm29 to hpm20. the weight of the lsb is 1tc. this setting applies in screen units. *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-44/106 29 command34 (subscreen: vertical di splay start position setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 0 5 - 1 4 - 1 command 3 identification code subscreen: vertical display start position setting 3 - 1 2 - 0 1 - 0 extended command 4 identification code 0 - 0 (2) second byte content da0 to 7 register state function notes 0 7 vps7 1 0 6 vps6 1 0 5 vps5 1 0 4 vps4 1 0 3 vps3 1 0 2 vps2 1 0 1 vps1 1 0 0 vps0 (lsb) 1 the vertical display start position, v ss , is given by: 8 v ss =1h ( 2 n vpsn) n=0 subscreen (wallpaper) the vertical display start position is specified by the 9 bits vps8 to vps0. the weight of the lsb is 1h. this setting applies in screen units. *: this resistor is set to the all bits zero state when the ic is reset by the rst pin. subscreen (wallpaper) display area hss v ss hsync vsync
lc74736pt no.a0569-45/106 30 command35 (subscreen: horizontal display start position setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 0 5 - 1 4 - 1 command 3 identification code subscreen: horizontal display start position setting 3 - 1 2 - 0 1 - 1 extended command 5 identification code 0 0 hps8 1 (2) second byte content da0 to 7 register state function notes 0 7 hps7 1 0 6 hps6 1 0 5 hps5 1 0 4 hps4 1 0 3 hps3 1 0 2 hps2 1 0 1 hps1 1 0 0 hps0 (lsb) 1 the horizontal display start position, hss, is given by: 9 hss=1tc ( 2 n hpsn)+ n=0 =15tc tc: the input clock frequency in operating mode. setting disable range qvga wvga sub h 1 character 00 to 13hex 00 to 22hex (00 to 1ahex) sub h 2 characters 00 to 1bhex 00 to 3ahex (00 to 2ahex) sub h 3 characters 00 to 23hex sub h 4 characters 00 to 2bhex the values in parentheses apply when rom access no. 2 and no. 3 are set. subscreen (wallpaper) the horizontal display start position is specified by the 9 bits hps9 to hps0. the weight of the lsb is 1tc. this setting applies in screen units. *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-46/106 31 command36 (screen background color: vertical display start position setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 0 5 - 1 4 - 1 command 3 identification code screen background color: vertical display start position setting 3 - 1 2 - 1 1 - 0 extended command 6 identification code 0 - 0 (2) second byte content da0 to 7 register state function notes 0 7 vpg7 1 0 6 vpg6 1 0 5 vpg5 1 0 4 vpg4 1 0 3 vpg3 1 0 2 vpg2 1 0 1 vpg1 1 0 0 vpg0 (lsb) 1 the vertical display start position, vsg, is given by: 8 vsg=1h ( 2 n vpgn) n=0 screen background color the vertical display start position is specified by the 8 bits vpg8 to vpg0. the weight of the lsb is 1h. this setting applies in screen units. *: this resistor is set to the all bits zero state when the ic is reset by the rst pin. vsync screen background color display area hsg vsg hsync
lc74736pt no.a0569-47/106 32 command37 (screen background color: ho rizontal display start position setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 0 5 - 1 4 - 1 command 3 identification code screen background color: horizontal display start position setting 3 - 1 2 - 1 1 - 1 extended command 7 identification code 0 0 hpg8 1 (2) second byte content da0 to 7 register state function notes 0 7 hpg7 1 0 6 hpg6 1 0 5 hpg5 1 0 4 hpg4 1 0 3 hpg3 1 0 2 hpg2 1 0 1 hpg1 1 0 0 hpg0 (lsb) 1 the horizontal display start position, hsg, is given by: 9 hsg=1tc ( 2 n hpgn) n=0 tc: the input clock frequency in operating mode. screen background color the horizontal display start position is specified by the 10 bits hpg9 to hpg0. the weight of the lsb is 1tc. this setting applies in screen units. *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-48/106 33 command40 (character size control setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 0 4 - 0 command 4 identification code character size control settings 3 - 0 2 - 0 1 - 0 0 - 0 extended command 0 identification code (2) second byte content da0 to 7 register state function notes 7 - 0 6 - 0 5 - 0 4 - 0 0 3 szv1 1 0 2 szv0 1 szv1 szv0 character size 0 0 1 0 1 2 1 0 3 1 1 4 specifies the character size in the vertical direction. this setting applies in line units. 0 1 szh1 1 0 0 szh0 1 szh1 szh0 character size 0 0 1 0 1 2 1 0 3 1 1 4 specifies the character size in the horizontal direction. this setting applies in line units. *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-49/106 34 command41 (character size line u control main 1 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 0 4 - 0 command 4 identification code character size line u control main 1 3 - 0 2 - 0 1 - 0 0 - 1 extended command 1 identification code (2) second byte content da0 to 7 register state function notes 0 do not set for line 8. 7 lsz7 1 set for line 8. 0 do not set for line 7. 6 lsz6 1 set for line 7. 0 do not set for line 6. 5 lsz5 1 set for line 6. 0 do not set for line 5. 4 lsz4 1 set for line 5. 0 do not set for line 4. 3 lsz3 1 set for line 4. 0 do not set for line 3. 2 lsz2 1 set for line 3. 0 do not set for line 2. 1 lsz1 1 set for line 2. 0 do not set for line 1. 0 lsz0 1 set for line 1. character size line setting control upper lines *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-50/106 35 command42 (character size line d control main 1 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 0 4 - 0 command 4 identification code character size line d control main 1 3 - 0 2 - 0 1 - 1 0 - 0 extended command 2 identification code (2) second byte content da0 to 7 register state function notes 0 do not set for line 16. 7 lsz15 1 set for line 16. 0 do not set for line 15. 6 lsz14 1 set for line 15. 0 do not set for line 14. 5 lsz13 1 set for line 14. 0 do not set for line 13. 4 lsz12 1 set for line 13. 0 do not set for line 12. 3 lsz11 1 set for line 12. 0 do not set for line 11. 2 lsz10 1 set for line 11. 0 do not set for line 10. 1 lsz9 1 set for line 10. 0 do not set for line 9. 0 lsz8 1 set for line 9. character size line setting control lower lines *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-51/106 36 command43 (character size line d2 control main 1 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 0 4 - 0 command 4 identification code character size line d2 control main 1 3 - 0 2 - 0 1 - 1 0 - 1 extended command 3 identification code (2) second byte content da0 to 7 register state function notes 7 - 0 6 - 0 5 - 0 4 - 0 3 - 0 2 - 0 0 do not set for line 18. 1 lsz17 1 set for line 18. 0 do not set for line 17. 0 lsz16 1 set for line 17. character size line setting control lower lines 2 *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-52/106 37 command44 (character size line u control main 2 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 0 4 - 0 command 4 identification code character size line u control main 2 3 - 0 2 - 1 1 - 0 0 - 0 extended command 4 identification code (2) second byte content da0 to 7 register state function notes 0 do not set for line 8. 7 lsz7 1 set for line 8. 0 do not set for line 7. 6 lsz6 1 set for line 7. 0 do not set for line 6. 5 lsz5 1 set for line 6. 0 do not set for line 5. 4 lsz4 1 set for line 5. 0 do not set for line 4. 3 lsz3 1 set for line 4. 0 do not set for line 3. 2 lsz2 1 set for line 3. 0 do not set for line 2. 1 lsz1 1 set for line 2. 0 do not set for line 1. 0 lsz0 1 set for line 1. character size line setting control upper lines *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-53/106 38 command45 (character size line d control main 2 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 0 4 - 0 command 4 identification code character size line d control main 2 3 - 0 2 - 1 1 - 0 0 - 1 extended command 5 identification code (2) second byte content da0 to 7 register state function notes 0 do not set for line 16. 7 lsz15 1 set for line 16. 0 do not set for line 15. 6 lsz14 1 set for line 15. 0 do not set for line 14. 5 lsz13 1 set for line 14. 0 do not set for line 13. 4 lsz12 1 set for line 13. 0 do not set for line 12. 3 lsz11 1 set for line 12. 0 do not set for line 11. 2 lsz10 1 set for line 11. 0 do not set for line 10. 1 lsz9 1 set for line 10. 0 do not set for line 9. 0 lsz8 1 set for line 9. character size line setting control lower lines *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-54/106 39 command46 (character size line d control main 2 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 0 4 - 0 command 4 identification code character size line d control main 2 3 - 0 2 - 1 1 - 1 0 - 0 extended command 6 identification code (2) second byte content da0 to 7 register state function notes 7 - 0 6 - 0 5 - 0 4 - 0 3 - 0 2 - 0 0 do not set for line 18. 1 lsz17 1 set for line 18. 0 do not set for line 17. 0 lsz16 1 set for line 17. character size line setting control lower lines 2 *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-55/106 46 command50 (box control: u setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 0 4 - 1 command 5 identification code box control u settings 3 - 0 2 - 0 extended command 0 identification code 1 - 0 0 - 0 (2) second byte content da0 to 7 register state function notes 0 7 bxl w1 1 0 6 bxl w0 1 w1 w0 0 0 1 dot 0 1 2 dots 1 0 3 dots 1 1 4 dots box display: left side dot width. this setting applies in line units. it does not depend on the character size. 0 5 bxu ct1 1 0 4 bxu ct0 1 bxuct1 0 0 0 color table number 1 0 1 color table number 2 1 0 color table number 3 1 1 color table number 4 box display: upper side color table specification this setting applies in line units. 0 3 bxu c3 1 0 2 bxu c2 1 0 1 bxu c1 1 0 0 bxu c0 1 box display: upper side color specification 0000 to 1111 0 to f (hexadecimal) box display: upper side color specification this setting applies in line units. *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-56/106 47 command51 (box control: d setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 0 4 - 1 command 5 identification code box control d settings 3 - 0 2 - 0 1 - 0 0 - 1 extended command 1 identification code (2) second byte content da0 to 7 register state function notes 0 7 bxr w1 1 0 6 bxr w0 1 w1 w0 0 0 1 dot 0 1 2 dots 1 0 3 dots 1 1 4 dots box display: right side dot width. this setting applies in line units. it does not depend on the character size. 0 5 bxd ct1 1 0 4 bxd ct0 1 bxdct1 0 0 0 color table number 1 0 1 color table number 1 1 0 color table number 3 1 1 color table number 4 box display: lower side color table specification this setting applies in line units. 0 3 bxd c3 1 0 2 bxd c2 1 0 1 bxd c1 1 0 0 bxd c0 1 box display: lower side color specification 0000 to 1111 0 to f (hexadecimal) box display: lower side color specification this setting applies in line units. *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-57/106 48 command52 (box control: u line main 1 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 0 4 - 1 command 5 identification code box control u line main 1 setting 3 - 0 2 - 0 1 - 1 0 - 0 extended command 2 identification code (2) second byte content da0 to 7 register state function notes 0 do not set for line 8. 7 lbx7 1 set for line 8. 0 do not set for line 7. 6 lbx6 1 set for line 7. 0 do not set for line 6. 5 lbx5 1 set for line 6. 0 do not set for line 5. 4 lbx4 1 set for line 5. 0 do not set for line 4. 3 lbx3 1 set for line 4. 0 do not set for line 3. 2 lbx2 1 set for line 3. 0 do not set for line 2. 1 lbx1 1 set for line 2. 0 do not set for line 1. 0 lbx0 1 set for line 1. box control line setting control upper lines *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-58/106 49 command53 (box control: d line main 1 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 0 4 - 1 command 5 identification code box control d line main 1 setting 3 - 0 2 - 0 1 - 1 0 - 1 extended command 3 identification code (2) second byte content da0 to 7 register state function notes 0 do not set for line 16. 7 lbx15 1 set for line 16. 0 do not set for line 15. 6 lbx14 1 set for line 15. 0 do not set for line 14. 5 lbx13 1 set for line 14. 0 do not set for line 13. 4 lbx12 1 set for line 13. 0 do not set for line 12. 3 lbx11 1 set for line 12. 0 do not set for line 11. 2 lbx10 1 set for line 11. 0 do not set for line 10. 1 lbx9 1 set for line 10. 0 do not set for line 9. 0 lbx8 1 set for line 9. box control line setting control lower lines *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-59/106 50 command54 (box control: d2 line main 1 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 0 4 - 1 command 5 identification code box control d2 line main 1 setting 3 - 0 2 - 1 1 - 0 0 - 0 extended command 4 identification code (2) second byte content da0 to 7 register state function notes 7 - 0 6 - 0 5 - 0 4 - 0 3 - 0 2 - 0 0 do not set for line 18. 1 lbx17 1 set for line 18. 0 do not set for line 17. 0 lbx16 1 set for line 17. box control line setting control lower lines *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-60/106 51 command55 (box control: u line main 2 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 0 4 - 1 command 5 identification code box control u line main 2 setting 3 - 0 2 - 1 1 - 0 0 - 1 extended command 5 identification code (2) second byte content da0 to 7 register state function notes 0 do not set for line 8. 7 lbx7 1 set for line 8. 0 do not set for line 7. 6 lbx6 1 set for line 7. 0 do not set for line 6. 5 lbx5 1 set for line 6. 0 do not set for line 5. 4 lbx4 1 set for line 5. 0 do not set for line 4. 3 lbx3 1 set for line 4. 0 do not set for line 3. 2 lbx2 1 set for line 3. 0 do not set for line 2. 1 lbx1 1 set for line 2. 0 do not set for line 1. 0 lbx0 1 set for line 1. box control line setting control upper lines *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-61/106 52 command56 (box control: d line main 2 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 0 4 - 1 command 5 identification code box control d line main 2 setting 3 - 0 2 - 1 1 - 1 0 - 0 extended command 6 identification code (2) second byte content da0 to 7 register state function notes 0 do not set for line 16. 7 lbx15 1 set for line 16. 0 do not set for line 15. 6 lbx14 1 set for line 15. 0 do not set for line 14. 5 lbx13 1 set for line 14. 0 do not set for line 13. 4 lbx12 1 set for line 13. 0 do not set for line 12. 3 lbx11 1 set for line 12. 0 do not set for line 11. 2 lbx10 1 set for line 11. 0 do not set for line 10. 1 lbx9 1 set for line 10. 0 do not set for line 9. 0 lbx8 1 set for line 9. box control line setting control lower lines *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-62/106 53 command57 (box control: d line main 2 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 0 4 - 1 command 5 identification code box control d2 line main 2 setting 3 - 0 2 - 1 1 - 1 0 - 1 extended command 7 identification code (2) second byte content da0 to 7 register state function notes 7 - 0 6 - 0 5 - 0 4 - 0 3 - 0 2 - 0 0 do not set for line 18. 1 lbx17 1 set for line 18. 0 do not set for line 17. 0 lbx16 1 set for line 17. box control line setting control lower lines 2 *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-63/106 54 command58 (line spacing control 1 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 0 4 - 1 command 5 identification code line spacing control 1 setting 3 - 1 2 - 0 1 - 0 0 - 0 extended command 8 identification code (2) second byte content da0 to 7 register state function notes 7 0 0 0 line spacing basic clock: 1v 6 gyb ck 1 line spacing basic clock: depending on the character size line spacing basic unit (clock) setting 0 5 gs1 1 0 4 gs0 1 gs1 gs0 character graphic 0 0 transparent transparent 0 1 transparent transparent 1 (char. bkg color) 1 (cb specified color) 1 0 char. bkg. color cb specified color 1 1 transparent transparent (border enabled) line spacing mode setting this setting applies in line units 0 3 gy3 1 0 2 gy2 1 0 1 gy1 1 0 0 gy0 1 gy3 2 1 0 line spacing ( h) 0 0 0 0 0 0 0 0 1 -1 (upper) +1 (lower) 0 0 1 0 -1 +2 0 0 1 1 -1 +3 0 1 0 0 -1 +4 0 1 0 1 -1 +5 0 1 1 0 -1 +6 0 1 1 1 -1 +7 1 0 0 0 -1 +8 1 0 0 1 -1 +9 1 0 1 0 -1 +10 1 0 1 1 -1 +11 1 1 0 0 -1 +12 1 1 0 1 -1 +13 1 1 1 0 -1 +14 1 1 1 1 -1 +15 line spacing dot number setting this setting applies in line units of 1h *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-64/106 55 command59 (line spacing control 2 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 0 4 - 1 command 5 identification code line spacing control 2 setting 3 - 1 2 - 0 1 - 0 0 - 1 extended command 9 identification code (2) second byte content da0 to 7 register state function notes 0 box display: lower side is 1 dot 7 bxw d 1 box display: lower side is 2 dots box display lower side. this setting applies in line units. depending on the character size 0 box display: upper side is 1 dot 6 bxw u 1 box display: upper side is 2 dots (invalid when line spacing is specified.) box display upper side. this setting applies in line units. depending on the character size 0 normal display 5 gyhsl 1 line spacing area: halftone line spacing area when halftone is specified this setting applies in line units. transparent is supported except for 00. 0 normal display 4 bxhsl 1 box area: halftone box area when halftone is specified this setting applies in line units 0 depending on the character 3 fchsl 1 depending on the character background border area when halftone is specified this setting applies in line units 0 displayed in upper part of character lower line spacing 2 bxc3 1 displayed in lower part of character lower line spacing box upper and lower display control 2 valid when line spacing is specified. this setting applies in line units 0 inside the character range (v1&v16 dots) 1 bxc2 1 outside the character range (line spacing area): valid only when line spacing is specified. box upper and lower display control 1 this setting applies in line units 0 inside the character range 0 bxc1 1 outside the character range box left and ight display control this setting applies in line units *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-65/106 56 command5a (line spacing control: u line main 1 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 0 4 - 1 command 5 identification code control the line spacing control line setting u main 1 3 - 1 2 - 0 1 - 1 0 - 0 extended command a identification code (2) second byte content da0 to 7 register state function notes 0 do not set for line 8. 7 lgy7 1 set for line 8. 0 do not set for line 7. 6 lgy6 1 set for line 7. 0 do not set for line 6. 5 lgy5 1 set for line 6. 0 do not set for line 5. 4 lgy4 1 set for line 5. 0 do not set for line 4. 3 lgy3 1 set for line 4. 0 do not set for line 3. 2 lgy2 1 set for line 3. 0 do not set for line 2. 1 lgy1 1 set for line 2. 0 do not set for line 1. 0 lgy0 1 set for line 1. control the line spacing control line setting upper lines *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-66/106 57 command5b (line spacing control: d line main 1 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 0 4 - 1 command 5 identification code control the line spacing control line setting d main 1 3 - 1 2 - 0 1 - 1 0 - 1 extended command b identification code (2) second byte content da0 to 7 register state function notes 0 do not set for line 16. 7 lgy15 1 set for line 16. 0 do not set for line 15. 6 lgy14 1 set for line 15. 0 do not set for line 14. 5 lgy13 1 set for line 14. 0 do not set for line 13. 4 lgy12 1 set for line 13. 0 do not set for line 12. 3 lgy11 1 set for line 12. 0 do not set for line 11. 2 lgy10 1 set for line 11. 0 do not set for line 10. 1 lgy9 1 set for line 10. 0 do not set for line 9. 0 lgy8 1 set for line 9. control the line spacing control line setting lower lines *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-67/106 58 command5c (line spacing control: d line main 1 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 0 4 - 1 command 5 identification code control the line spacing control line setting d main 1 3 - 1 2 - 1 1 - 0 0 - 0 extended command c identification code (2) second byte content da0 to 7 register state function notes 7 - 0 6 - 0 5 - 0 4 - 0 3 - 0 2 - 0 0 do not set for line 18. 1 lgy17 1 set for line 18. 0 do not set for line 17. 0 lgy16 1 set for line 17. control the line spacing control line setting lower lines 2 *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-68/106 59 command5d (line spacing control: u line main 2 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 0 4 - 1 command 5 identification code control the line spacing control line setting u main 2 3 - 1 2 - 1 1 - 0 0 - 1 extended command d identification code (2) second byte content da0 to 7 register state function notes 0 do not set for line 8. 7 lgy7 1 set for line 8. 0 do not set for line 7. 6 lgy6 1 set for line 7. 0 do not set for line 6. 5 lgy5 1 set for line 6. 0 do not set for line 5. 4 lgy4 1 set for line 5. 0 do not set for line 4. 3 lgy3 1 set for line 4. 0 do not set for line 3. 2 lgy2 1 set for line 3. 0 do not set for line 2. 1 lgy1 1 set for line 2. 0 do not set for line 1. 0 lgy0 1 set for line 1. control the line spacing control line setting upper lines *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-69/106 60 command5e (line spacing control: d line main 2 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 0 4 - 1 command 5 identification code control the line spacing control line setting d main 2. 3 - 1 2 - 1 1 - 1 0 - 0 extended command e identification code (2) second byte content da0 to 7 register state function notes 0 do not set for line 16. 7 lgy15 1 set for line 16. 0 do not set for line 15. 6 lgy14 1 set for line 15. 0 do not set for line 14. 5 lgy13 1 set for line 14. 0 do not set for line 13. 4 lgy12 1 set for line 13. 0 do not set for line 12. 3 lgy11 1 set for line 12. 0 do not set for line 11. 2 lgy10 1 set for line 11. 0 do not set for line 10. 1 lgy9 1 set for line 10. 0 do not set for line 9. 0 lgy8 1 set for line 9. control the line spacing control line setting lower lines *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-70/106 61 command5f (line spacing control: d line main 2 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 0 4 - 1 command 5 identification code control the line spacing control line setting d main 2. 3 - 1 2 - 1 1 - 1 0 - 1 extended command f identification code (2) second byte content da0 to 7 register state function notes 7 - 0 6 - 0 5 - 0 4 - 0 3 - 0 2 - 0 0 do not set for line 18. 1 lgy17 1 set for line 18. 0 do not set for line 17. 0 lgy16 1 set for line 17. control the line spacing control line setting lower lines *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-71/106 62 command60 (border control setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 1 4 - 0 command 6 identification code border control setting 3 - 0 2 - 0 1 - 0 0 - 0 extended command 0 identification code (2) second byte content da0 to 7 register state function notes 0 7 blk1 1 0 6 blk0 1 blk1 blk0 border mode specification 0 0 normal display 0 1 border 1 0 shadow 1 (lower side) 1 1 shadow 2 (lower and right sides) border mode specification this setting applies in line units. 0 5 eg ct1 1 0 4 eg ct0 1 egct1 0 0 0 color table number 1 0 1 color table number 2 1 0 color table number 3 1 1 color table number 4 border display color table specification this setting applies in line units. 0 3 eg c3 1 0 2 eg c2 1 0 1 eg c1 1 0 0 eg c0 1 border display: color specification 0000 to 1111 0 to f (hexadecimal) border display color specification this setting applies in line units. *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-72/106 63 command61 (border control u line main 1 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 1 4 - 0 command 6 identification code border line setting u main 1 control 3 - 0 2 - 0 1 - 0 0 - 1 extended command 1 identification code (2) second byte content da0 to 7 register state function notes 0 do not set for line 8. 7 lfc7 1 set for line 8. 0 do not set for line 7. 6 lfc6 1 set for line 7. 0 do not set for line 6. 5 lfc5 1 set for line 6. 0 do not set for line 5. 4 lfc4 1 set for line 5. 0 do not set for line 4. 3 lfc3 1 set for line 4. 0 do not set for line 3. 2 lfc2 1 set for line 3. 0 do not set for line 2. 1 lfc1 1 set for line 2. 0 do not set for line 1. 0 lfc0 1 set for line 1. border control line settings control main 1 upper lines *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-73/106 64 command62 (border control d line main 1 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 1 4 - 0 command 6 identification code border line setting d main 1 control 3 - 0 2 - 0 1 - 1 0 - 0 extended command 2 identification code (2) second byte content da0 to 7 register state function notes 0 do not set for line 16. 7 lfc15 1 set for line 16. 0 do not set for line 15. 6 lfc14 1 set for line 15. 0 do not set for line 14. 5 lfc13 1 set for line 14. 0 do not set for line 13. 4 lfc12 1 set for line 13. 0 do not set for line 12. 3 lfc11 1 set for line 12. 0 do not set for line 11. 2 lfc10 1 set for line 11. 0 do not set for line 10. 1 lfc9 1 set for line 10. 0 do not set for line 9. 0 lfc8 1 set for line 9. border control line settings control main 1 lower lines *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-74/106 65 command63 (border control d line main 1 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 1 4 - 0 command 6 identification code border line setting d main 1 control 3 - 0 2 - 0 1 - 1 0 - 1 extended command 3 identification code (2) second byte content da0 to 7 register state function notes 7 - 0 6 - 0 5 - 0 4 - 0 3 - 0 2 - 0 0 do not set for line 18. 1 lfc17 1 set for line 18. 0 do not set for line 17. 0 lfc16 1 set for line 17. border control line settings control main 1 lower lines *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-75/106 66 command64 (border control u line main 2 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 1 4 - 0 command 6 identification code border line setting u main 2 control 3 - 0 2 - 1 1 - 0 0 - 0 extended command 4 identification code (2) second byte content da0 to 7 register state function notes 0 do not set for line 8. 7 lfc7 1 set for line 8. 0 do not set for line 7. 6 lfc6 1 set for line 7. 0 do not set for line 6. 5 lfc5 1 set for line 6. 0 do not set for line 5. 4 lfc4 1 set for line 5. 0 do not set for line 4. 3 lfc3 1 set for line 4. 0 do not set for line 3. 2 lfc2 1 set for line 3. 0 do not set for line 2. 1 lfc1 1 set for line 2. 0 do not set for line 1. 0 lfc0 1 set for line 1. border control line settings control main 2 upper lines *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-76/106 67 command65 (border control d line main 2 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 1 4 - 0 command 6 identification code border line setting d main 2 control 3 - 0 2 - 1 1 - 0 0 - 1 extended command 5 identification code (2) second byte content da0 to 7 register state function notes 0 do not set for line 16. 7 lfc15 1 set for line 16. 0 do not set for line 15. 6 lfc14 1 set for line 15. 0 do not set for line 14. 5 lfc13 1 set for line 14. 0 do not set for line 13. 4 lfc12 1 set for line 13. 0 do not set for line 12. 3 lfc11 1 set for line 12. 0 do not set for line 11. 2 lfc10 1 set for line 11. 0 do not set for line 10. 1 lfc9 1 set for line 10. 0 do not set for line 9. 0 lfc8 1 set for line 9. border control line settings control main 2 lower lines *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-77/106 68 command66 (border control d line main 2 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 1 4 - 0 command 6 identification code border line setting d main 2 control 3 - 0 2 - 1 1 - 1 0 - 0 extended command 6 identification code (2) second byte content da0 to 7 register state function notes 7 - 0 6 - 0 5 - 0 4 - 0 3 - 0 2 - 0 0 do not set for line 18. 1 lfc17 1 set for line 18. 0 do not set for line 17. 0 lfc16 1 set for line 17. border control line settings control main 2 lower lines *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-78/106 69 command67 (pll control 1 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 1 4 - 0 command 6 identification code pll control 1 3 - 0 2 - 1 1 - 1 0 - 1 extended command 7 identification code (2) second byte content da0 to 7 register state function notes 0 external vco on 7 evo off 1 external vco off 0 lc oscillator on 6 lc off 1 lc oscillatior off 0 external clock on 5 eck off 1 external clock off 0 vco oscillator on 4 vco off 1 vco oscillator off oscillator-related control initial lc oscillation 0 3 vco sl1 1 0 2 vco sl0 1 vcosl1 0 0 0 internal vco 1/1 0 1 internal vco 1/2 1 0 internal vco 1/4 1 1 external vco vco selection clock selection required cksl = 10 0 1 cksl 1 1 0 0 cksl 0 1 cksl1 0 0 0 lc 0 1 external clock 1 0 internal vco (pll) or external vco clock selection *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-79/106 70 command68 (pll control 2 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 1 4 - 0 command 6 identification code pll control 2 3 - 1 2 - 0 1 - 0 0 - 0 extended command 8 identification code (2) second byte content da0 to 7 register state function notes 7 - 0 6 - 0 5 - 0 0 4 div 12 1 0 3 div 11 1 0 2 div 10 1 0 1 1 div 9 1 0 0 div 8 1 pll-circuit frequency division ratio setting *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-80/106 71 command69 (pll control 3 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 1 4 - 0 command 6 identification code pll control 3 3 - 1 2 - 0 1 - 0 0 - 1 extended command 9 identification code (2) second byte content da0 to 7 register state function notes 0 7 div 7 1 0 6 div 6 1 0 5 div 5 1 0 4 div 4 1 0 3 div 3 1 0 2 div 2 1 0 1 div 1 1 0 0 div 0 1 12 n2= 2 n divn n=0 n2: 48 to 8196 30 to 1fff (hexadecimal) fvco = fh n2 vco oscillation frequency horizontal frequency input pll-circuit frequency division ratio setting initial values: 27bhex fh = 15.734khz fvco = 10mhz *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-81/106 72 command6a (pll control 5 setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 1 4 - 0 command 6 identification code pll control 5 3 - 1 2 - 0 1 - 1 0 - 0 extended command a identification code (2) second byte content da0 to 7 register state function notes 7 - 0 0 hd (afc) 6 hd sel 1 hin (input) h sync signal switch at afc enabled when com67-2 cksl is set to 10. 0 5 dz1 1 0 4 dz0 1 dz1 dz0 0 0 dza 0.0ns 0 1 dzb 0.5ns 1 0 dzc 2.5ns dead zone specification 0 href (sync) 3 href sl 1 href (directly) href selection 0 2 did 2 1 0 1 did 1 1 0 0 did 0 1 did2 1 0 frequency division ratio (n1) 0 0 0 1/1 0 0 1 1/2 0 1 0 1/3 0 1 1 1/4 1 0 0 1/6 fdot = fvco n1 dot clock vco oscillation frequency dot clock frequency division ratio specification *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-82/106 73 command6c0 (color table write address setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 1 4 - 0 command 6 identification code color table write address setting 3 - 1 2 - 1 1 - 0 0 - 0 sub-identifier code co (2) second byte content da0 to 7 register state function notes 7 - 6 - 0 5 ctn1 1 0 4 ctn0 1 ctn1 ctn0 0 0 color table number 1 0 1 color table number 2 1 0 color table number 3 1 1 color table number 4 color table selection 0 3 cta3 (msb) 1 0 2 cta2 1 0 1 cta1 1 0 0 cta0 (lsb) 1 color table address 0 to 15 0 to f (hexadecimal) 16 values address of the color tables *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-83/106 74 command6c1 (color table data write setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 1 4 - 0 command 6 identification code color table write setting when this command has been issued, the ic remains in display character data write mode until the cs pin is set high. 3 - 1 2 - 1 1 - 1 sub-identifier code c1 0 0 rm3 1 rm3 mode 0 [1][2] end 1 [1][2] continuous continuous write mode selection (2) second byte-[1] content da0 to 7 register state function notes 7 - 0 6 - 0 0 halftone: off 5 hft 1 halftone: on (hftot output is high.) 0 color 4 tok 1 transparent (blk output: low) 0 3 tb3 1 0 2 tb2 1 0 1 tb1 1 0 0 tb0 1 color table b output 0000 to 1111 0 to f (hexadecimal) color table setting b *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-84/106 (3) second byte-[2] content da0 to 7 register state function notes 0 7 tg3 1 0 6 tg2 1 0 5 tg1 1 0 4 tg0 1 color table g output 0000 to 1111 0 to f (hexadecimal) color table setting g 0 3 tr3 1 0 2 tr2 1 0 1 tr1 1 0 0 tr0 1 color table r output 0000 to 1111 0 to f (hexadecimal) color table setting r *: this resistor is set to the all bits zero state when the ic is reset by the rst pin. when transparent is selected, the blk output is set to the low level. (transparent state) the rgb outputs are values from the color table. the transparent specification is best for color table 1, address 0000. since the data is set to all zeros by a ram clear operation, the rgb output will be 000 (black) and the blk output will be 1. transparent is specified by setting the tok bit to 1. (the blk output will go to the low level.)
lc74736pt no.a0569-85/106 75 command700 (character ram write address setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 1 4 - 1 command 7 identification code character ram write address setting 3 - 0 2 - 0 1 - 0 0 - 0 sub-identifier code 000 (2) second byte content da0 to 7 register state function notes 0 7 fad1 1 0 6 fad0 1 qvga mode character ram address 0 to 3 0 to 3 (hexadecimal) wvga mode pno. 0 to 3 p1 to p4 character ram qvga: address wvga: pno. 0 5 frn1 1 0 4 frn0 1 rom no.1 to 4 0 to 3 0 to 3 (hexadecimal) no.1 to no.4 character ram rom no. 0 3 fva3 (msb) 1 0 2 fva2 1 0 1 fva1 1 0 0 fva0 (lsb) 1 character ram v dot addresses 0 to 15 0 to f (hexadecimal) character ram v dot address *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-86/106 76 command701 (character ra m data write setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 1 4 - 1 command 7 identification code character ram data write address setting when this command has been issued, the ic remains in display character data write mode until the cs pin is set high. 3 - 0 2 - 0 1 - 1 sub-identifier code 001 0 0 rm3 1 rm3 mode 0 [1][2] end 1 [1][2] continuous continuous write mode selection (2) second byte-[1] content da0 to 7 register state function notes 0 7 d15 1 0 6 d14 1 0 5 d13 1 0 4 d12 1 0 3 d11 1 0 2 d10 1 0 1 d9 1 0 0 d8 1 character ram write data d15 to d0 character ram write data *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-87/106 (3) second byte-[2] content da0 to 7 register state function notes 0 7 d7 1 0 6 d6 1 0 5 d5 1 0 4 d4 1 0 3 d3 1 0 2 d2 1 0 1 d1 1 0 0 d0 1 character ram write data *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-88/106 77 command710 (wvga: rom access setting command) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 1 4 - 1 command 7 identification code wvga rom access setting 3 - 0 2 - 1 1 - 0 0 - 0 sub-identifier code 0100 (2) second byte content da0 to 7 register state function notes 7 0 6 0 0 5 ckos1 1 0 4 ckos0 1 ckos1 0 0 0 clk 0 1 phasecp(hd1bfq) 1 0 nchcp 1 1 pchcp clkout output selection 0 no border 3 wfcmd 1 border (displayed for each upper and lower 1v) wvga mode specifies border display when rom access mode is set to 011 or 100. 0 2 wram2 1 0 1 wram1 1 0 0 wram0 1 when wram210 dclk=33.3mhz ? no.1 3clk = 90ns 000 main 1 only (main 2 display off) 001 main 2 only (main 1 display off) because box is displayed ? no.2 2clk 60ns main 1 main 2 010 character character 011 graphic character hpm1 hpm2 * the character has no border. 100 character graphic hpm1 hpm2 * the character has no border. ? no.3 1clk = 30ns 101 equivalent to qvga (external rom only) wvga mode rom access specification *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-89/106 78 command711 (pll setting command 6) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 1 4 - 1 command 7 identification code pll setting command 6 3 - 0 2 - 1 1 - 0 0 - 1 sub-identifier code 0101 (2) second byte content da0 to 7 register state function notes 0 vcor: internal rsetb"h" 7 rsetb 1 vcor: external "l" vcor selection 6 - 0 0 5 vcr s1 1 0 4 vcr s0 1 vcrs1 vcrs0 rset0 1 2 0 0 5.6k 1 1 0 0 1 6.6k 1 0 0 1 0 7.6k 0 0 0 1 1 4.6k 1 1 1 internal vcor value setting large resistance low gain 0 the following set current 1 3 cpi x2 1 the following set current 3 cp current value setting 2 2 - 0 0 1 cpi s1 1 0 0 cpi s0 1 cpis1 cpis0 cpis0 1 2 0 0 40 a 0 0 0 0 1 44 a 1 0 0 1 0 52 a 0 1 0 1 1 60 a 0 0 1 cp current value setting 1 *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-90/106 79 command712 (pll setting command 7) (1) first byte content da0 to 7 register state function notes 7 - 1 6 - 1 5 - 1 4 - 1 command 7 identification code display character data write setting 3 - 0 2 - 1 1 - 1 0 - 0 sub-identifier code 0110 (2) second byte content da0 to 7 register state function notes 7 - 0 0 normal operation: styb"h" 6 styb cp 1 cp, vco standby: pd0 = "z" cp, vco standby setting 0 normal operation: resetb"h" 5 resetbcp 1 pd reset: pd0 = "z" pd reset setting 0 cp enable: scp1"h" 4 scp1 cp 1 cp disable cp control 0 normal operation: divenb"h" 3 div enb 1 frequency divider reset frequency divider control 0 2 gain 2 1 0 1 gain 1 1 0 0 gain 0 1 gain fmin fmax gain[mhz] 2 1 0 0 0 0 7 40 20/v 0 0 1 7 -20% -22.5% 0 1 0 -20% 40 +2.5% 0 1 1 -20% -20% -20% 1 0 0 +20% +10% +8.75% 1 0 1 +20% -10% -13.75% 1 1 0 7 +10% +11.25% 1 1 1 7 -10% +11.25% vco adjustment *: this resistor is set to the all bits zero state when the ic is reset by the rst pin.
lc74736pt no.a0569-91/106 display structure the display screen consists of a 34-character 18-line grid (maximum). ? qvga mode (16 16 dot characters) qvga panel (480 234) 30-character 15-line ? wvga mode (24 32 dot characters) wvga panel (800 480) 33-character 15-line up to a maximum of 612 ch aracters can be displayed. if the character size is increased, the number of characters th at can be displayed will decrease to be fewer than 612 characters. display memory is addressed by specifying a line addr ess (00 to 17 (hexadecimal) and a character position address (00 to 32 (hexadecimal)). display memory is addressed by specifying a line addr ess (00 to 11 (hexadecimal) and a character position address (00 to 21 (hexadecimal)). display structure (display me mory address): 34 characters 18 lines (maximum) 00 33 00 21
lc74736pt no.a0569-92/106 operational description 1. command transfer method 1.1 overview (1) commands are transferred in 8-bit units, lsb first. always send a first byte and a second byte (16 bits). (2) command10 (main screen 1 ram write) command11 (main screen 2 ram write) command12 (subscreen write) commnad6c1 (color table write) command701 (character ram write) is locked in continuous write mode when a continuous mode is specified (rm2, 1 rm3). (continuous mode is cleared by setting the cs pin high.) 1.2 writing data to vram (1) write start address specification write start address is set using: command00, command01 (main screen 1) command02, command03 (main screen 2) command04 (subscreen) v4 to v0: vertical direction; h5 to h0: horizontal direction (2) data write continuous write mode differs depending on the write mode specification. (rm1, rm2) 1. normal (rm2 = 0, rm1 = 0: initial state) *continuous mode not used* -- com10-1 10-2-1 10-2-2 10-2-3 10-2-4 10-2-5 command wait state -- 2. write continuous (rm2 = 0, rm1 = 1): mode 2 com10-1 10-2-1 10-2-2 10-2-3 10-2-4 10-2-5 3. write continuous (rm2 = 1, rm1 = 0): mode 3 com10-1 10-2-1 10-2-2 10-2-3 10-2-4 10-2-5 10-2-3 10-2-4 10-2-5 4. write continuous (rm2 = 1, rm1 = 1): mode 4 com10-1 10-2-1 10-2-2 10-2-3 10-2-4 10-2-5 10-2-2 10-2-3 10-2-4 10-2-5 *: in modes 2, 3, and 4, the ic remains locked in continuous write mode until the cs pin is set high. ? the write address is automatically incremented. ? the write address is retained unless the ic is reset or a new write address is issued.
lc74736pt no.a0569-93/106 1.3 color table write (1) write start address specification use command 6c0 to set the color table write start address. ctn1 to ctn0: color table specification (no.1 to no.4), cta3 to cta0: address specification no.1 b g r 0 0 0 0 xx xxxx xxxx xxxx 0 0 0 1 0 0 1 0 address 1 1 1 0 1 1 1 1 (2) data write continuous write mode differs depending on the write mode specification. (rm3) 1. normal (rm3 = 0: initial state) *continuous mode not used* ---com6c1-1 6c1-2-1 6c1-2-2 command wait state --- 2. write continuous (rm3 = 1) mode com6c1-1 6c1-2-1 6c1-2-2 *: in mode 2, the ic remains locked in continuous write mode until the cs pin is set high. ? the write address is automatically incremented. ? the write address is retained unless the ic is reset or a new write address is issued.
lc74736pt no.a0569-94/106 1.4 character ram write (1) write start address specification use command700 to specify the char acter ram write start address. fad1to fad0: character ram address p-no specification qvga: 0 to 3, hexadeci mal, (4 characters) wvga: 1 character only 0 to 3 (hexadecimal) p1 to p4 fva3 to fva0: character ram v dot addre ss specificatrion 0 to f (hexadecimal) frn1 to frn0: rom no. specification 0 to 3 (hexadecimal) no.1 to no.4 d15 to d0 0 0 0 0 0 0 0 1 0 0 1 0 v dot address 1 1 1 0 1 1 1 1 (2) data write continuous write mode differs depending on the write mode specification. (rm3) 1. normal (rm3 = 0: initial state) *continuous mode not used* ---com701-1 701-2-1 701-2-2 command wait state --- 2. write continuous (rm3 = 1) mode com701-1 701-2-1 701-2-2 *: in mode 2, the ic remains locked in continuous write mode until the cs pin is set high. ? the write address is automatically incremented. ? the write address is retained unless the ic is reset or a new write address is issued.
lc74736pt no.a0569-95/106 2. display format 2.1 color specification related items (1) when a character is specified specify color with the character color (chara cter area) and character background color (outside the character area) character color: 1 of 16 colors character background color: 1 of 16 colors color tables: table no. 1 to no. 4 specified by ct1 to ct0. (com10-2-3: vram) 1 of 64 types character color character background color specified by cc0 to cc3: 1of 16 colors specified by cb0 to cb3: 1 of 16 colors (com10-2-2: vram) (com10-2-2: vram) (2) when a graphic 1 is specified specify color is in dot units (16 16) 1 of 16 colors (from) color tables: table no. 1 to no. 4 specified by ct1 to ct0. (com10-2-3: vram) 1 of 64 types specified by from: 1 of 16 types
lc74736pt no.a0569-96/106 (3) when a graphic 2 is specified specify color is in dot units (16 16) 1 of 16 colors (from) color tables: table no. 1 to no. 4 specified by ct1 to ct0. (com10-2-3: vram) 1 of 64 types the ctb address display color shown with cb3 to cb0 is changed to the ctb address display color shown with cc3 to cc0. one color in the graphic character display can be changed by setting cb and cc. specified by from: 1 of 16 types (4) when a graphic 3 is specified specify color is in dot units (16 16) 1 of 16 colors (from) color tables: table no. 1 to no. 4 specified by ct1 to ct0. (com10-2-3: vram) 1 of 64 types ctb no. in the address shown with cb3 to cb0 is changed to ctb no. shown with cc1 to cc0 and display it. ctb no. of one color in the graphic character display can be changed by setting cb and cc. specified by from: 1 of 16 types
lc74736pt no.a0569-97/106 2.2 display control related items (1) blinking: in character units 1. normal at1 = 0 (com10-2-1: vram) 2. blinking at1 = 1 display alternates between normal and transparent with the blinking period. (com21-2: bk1, bk0) (2) border display: only valid for font specified characters 1. border color: 1 of 16 colors (com60-2 egc3 to egc0) color table specification (com60-2 egct1 to egct0) 1 of 64 types specified in line units 2. border mode control (com60-2 blk1, blk0) specified in line units i. border ii. shadow 1: lower iii. shadow 2: lower + right
lc74736pt no.a0569-98/106 (3) character size: specified in line units the character size is specified as 1x to 4x indepe ndently for the vertical an d horizontal directions. (com40-2) 2.3 box display (raised/recessed) raised recessed 16 dots 16 dots (1) raised/recessed specification: in character units (com10-2-1 bxs) (2) left side-displayed/undis played specification: in char acter units (com10-2-1 bxl) (3) right side-displayed/undis played specification: in char acter units (com10-2-1 bxr) (4) upper side-displayed/undis played specification: in char acter units (com10-2-1 bxu) (5) lower side-displayed/undis played specification: in char acter units (com10-2-1 bxd) (6) color specification: in line units com50 (upper side) com51 (lower side) bxuc3 to bxdc0: 1 of 16 colors bxdc3 to bxdc0: 1 of 16 colors color table specification bxuct1 to bxuct0 bxdct1 to bxuct0 1 of 64 types box dot width specification each of left, right, upper, and lower can be specified independently. left: bxlw1 to bx lw0 1 to 4 dots right: bxrw1 to bxrw0 1 to 4 dots upper and lower (com59-2) upper bxwu 1 to 2 dots (it depends on the character size.) lower bxwd 1 to 2 dots (it depends on the character size.)
lc74736pt no.a0569-99/106 2.4 line spacing control (command 58-2: gy3, gy2, gy1, gy0) ? line spacing display control com58-2: gs1, gs0 character graphic (1) transparent transparent (2) transparent transparent 1(character back ground color) 1(cb specified color) (3) character background color cb setting color (4) transparent transparent (border enabled) 16 dots +1 to +15 line spacing 16 dots -1 16 dots -1 16 dots 16 dots +1 to +15 line spacing 16 dots -1 +1 to +15
lc74736pt no.a0569-100/106 ? basic line spacing unit gybck "0": 1v "1": it depends on the character size. ? box display (com59-2) character display range 16 16 box display inside the character outside the character 1 (valid only when line spacing is set.) outside the character 2 (valid only when line spacing is set.) bxc1 = "0" bxc1 = "1" bxc1 = "1" bxc2 = "0" bxc2 = "1" bxc2 = "1" bxc3 = "0" bxc3 = "1"
lc74736pt no.a0569-101/106 2.5 screen structure screen background color wallpaper display screen main screen 2 16 16 dot characters 30-character 15-line qvga panel main screen 1 16 16 dot characters 30-character 15-line ? for each screen: display on/off (trans parent) can be specified independently. ? for each screen: the display start pos ition can be specified independently. the wallpaper display screen and the main screen require xxxx clocks before the horizontal start position is reached.
lc74736pt no.a0569-102/106 ? display format 1) qvga 2) wvga ? rom structure (1) no internal rom (2) internal character ram qvga: 4 characters, wvga: 1 character 1) character font qvga: 16 16-dot structure wvga: 24 32-dot structure 2) graphics qvga: 16 16-dot structure wvga: 24 32-dot structure character specification 16 dots graphic 16 dots 16h graphic 24 dots character specification 24 dots 32h
lc74736pt no.a0569-103/106 (3) external rom (qvga: 16384 ch aracters, wvga: 4096 characters) 16 types, 16m 1) conditions ? qvga mode access time = 2 dot clock frequency or shorter example: dclk = 10mhz = 100ns 2 = 200ns or shorter ? wvga mode 1) access time =3 dot clock frequency or shorter, with display limitations example: dclk = 33mhz = 30ns 3 = 90ns or shorter 2) access time =2 dot clock frequency or shorter, with display limitations example: dclk = 33mhz = 30ns 2 = 60ns or shorter 3) access time =1 dot clock frequency or shorter example: dclk = 33mhz = 30ns 1 = 30ns or shorter 2) rom map ? qvga ? address ? data a19 to a0 d15 to d0 used a19 to a6 (14 bits) = 16384 characters = character codes color information 11 10 01 00 16 dots n4 n3 n2 n1 16 dots a 5 to a2 a 1 to a0
lc74736pt no.a0569-104/106 ? wvga ? address ? data a19 to a0 d15 to d12, d11 to d0 unused used on each of p1 to p4 a19 to a8 (12 bits) = 4096 characters = character codes 16 dots 16 dots p1 00 p2 01 12 dots 12 dots p3 10 p4 11 a 3 to a2 location information color information 11 10 01 00 12 dots n4 n3 n2 n1 16 dots a 7 to a4 a 1 to a0
lc74736pt no.a0569-105/106 3) display appearance ? qvga: 1 character = 16 16 dots character n1 or n2 or n3 or n4, vram selectable graphic n1+n2+n3+n4 character graphic ? wvga: 1 character = 24 32 dots character p1+p2+p3+p4 (12 16 4) n1 or n2 or n3 or n4, vram selectable graphic p1+p2+p3+p4 (12 16 4) n1+n2+n3+n4 character graphic 12 12 16 p1 p2 16 16 p3 p4 16 12 12 n1+n2 +n3+n4 n1 or n2 or n3 or n4 16 16 16 16 n1+n2 +n3+n4 n1 or n2 or n3 or n4 24 24 32 32
lc74736pt no.a0569-106/106 ps this catalog provides informati on as of june, 2007. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probabi lity. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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